Table of Contents

1. About

This project builds up a RISC-V server reference platform to address common challenges faced by SOC vendors in developing platform firmware products, thereby minimizing redundant tasks across the board.

2. Server SOC Reference Model

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3. Boot Execution

Command example1:

./qemu-system-riscv64 -nographic -m 8G -smp 2 \
 -machine rvsp-ref,pflash0=pflash0,pflash1=pflash1 \
 -blockdev node-name=pflash0,driver=file,read-only=on,filename=$FW_DIR/RISCV_SP_CODE.fd \
 -blockdev node-name=pflash1,driver=file,filename=$FW_DIR/RISCV_SP_VARS.fd \
 -bios $Sbi_DIR/fw_dynamic.bin \
 -drive file=$Img_DIR/brs_live_image.img,if=ide,format=raw

...

   Step 1.1:  change common/scripts/get_source.sh 

get_edk2_src()
{
    gitclone--depth1--single-branch\
    --branchedk2-stable202308https://github.com/tianocore/edk2.git
    pushd $TOP_DIR/edk2

    gitsubmoduleupdate--init

    popd

    gitclone--depth1--single-branch\
    --branch masterhttps://github.com/tianocore/edk2-platforms.git
    pushd $TOP_DIR/edk2-platforms

    gitsubmoduleupdate--init
    popd
}

 Step 1.2:  change brsi/scripts/build-scripts/start_qemu.sh

build_edk2()
{
    if [ !-d"$TOP_DIR/edk2" ];then
        source./build-scripts/get_brsi_source.sh
        source./build-scripts/build_brsi.sh
        source./build-scripts/build_image.sh
    fi
    if [ -f"$TOP_DIR/Build/RiscVQemuServerPlatform/${UEFI_BUILD_MODE}_${UEFI_TOOLCHAIN}/FV/RISCV_SP_CODE.fd" ];then
        echo"skip build edk2."
    else
        echo"build edk2..."
        pushd $TOP_DIR
        exportGCC5_RISCV64_PREFIX=riscv64-linux-gnu-
        exportPACKAGES_PATH=$TOP_DIR/edk2
        exportEDK_TOOLS_PATH=$TOP_DIR/edk2/BaseTools
        sourceedk2/edksetup.sh
        make-Cedk2/BaseToolsclean
        make-Cedk2/BaseTools
        make-Cedk2/BaseTools/Source/C
        sourceedk2/edksetup.shBaseTools
        build-aRISCV64--buildtarget ${UEFI_BUILD_MODE} -pPlatform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.dsc-t ${UEFI_TOOLCHAIN}
        truncate-s32MBuild/RiscVQemuServerPlatform/${UEFI_BUILD_MODE}_${UEFI_TOOLCHAIN}/FV/RISCV_SP_CODE.fd
        truncate-s32MBuild/RiscVQemuServerPlatform/${UEFI_BUILD_MODE}_${UEFI_TOOLCHAIN}/FV/RISCV_SP_VARS.fd
        popd
    fi
}

continue to follow the remaining steps in the README.md,   start from executing './build-scripts/build_brsi.sh' and './build-scripts/build_image.sh'.

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2.  Run a combined script for Boot and test functions

 ./build-scripts/start_qemu.sh

4.3 Verification

The tests covered in this document are based on the BRS spec, focusing on two primary modules: SCT and FWTS. The relevant test scripts, pre-build image and guidance can be obtained from the RISC-V BRS Development Suite Repository.


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========================================================================================================================================================================

References

Server Soc Specification: https://github.com/riscv-non-isa/server-soc

Server Platform Specification: https://github.com/riscv-non-isa/riscv-server-platform

BRS Specification: https://github.com/riscv-non-isa/riscv-brs 

Boot Flow: EDK2 implementation choices for RISC-V platforms.pdf

RISC-V BRS Development Suite Repository: https://github.com/intel/rv-brs-test-suite

Project Scope and Timelines

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