| Topic ID | Topic Name | Company | Contact | Comments |
| EDK2 | ||||
| EDK2_00_01 | MultiArchUefiPkg | Intel | Andrei Warkentin <andrei.warkentin@intel.com> | OpRom Emulator https://github.com/intel/MultiArchUefiPkg |
| EDK2_00_02 | StandaloneMmPkg | Intel, Ventana | Andrei Warkentin <andrei.warkentin@intel.com> Tuan Phan <tphan@ventanamicro.com> | Port of Tiano StandaloneMmPkg to various envos (raw M mode using OpenSBI, TEE using Salus/Penglai/etc) to support authenticated variable store and other scenarios. |
| EDK2_00_03 | FdtBusDxe | Intel | Andrei Warkentin <andrei.warkentin@intel.com> | DT-driven driver binding for Tiano, similar to what U-Boot does today. |
| EDK2_00_04 | Build size | Intel | Andrei Warkentin <andrei.warkentin@intel.com> | LTO and other size optimization with current compilers. |
| EDK2_00_05 | Tiano backtracing | Intel | Andrei Warkentin <andrei.warkentin@intel.com> | Useful crash information without a debugger across GCC and Clang (when available). Possibly depends on tool work. |
| EDK2_00_06 | SSTC support | Ventana | Sunil V L <sunilvl@ventanamicro.com> | Currently EDK2 uses SBI for timer implementation. Enhance to use SSTC if available. |
| EDK2_00_07 | Clang support | Ventana | Sunil V L <sunilvl@ventanamicro.com> | Currently only GCC is supported for RISC-V EDK2. Add clang support. |
| EDK2_00_08 | Basic MMU support | Ventana | Tuan Phan <tphan@ventanamicro.com> | Add basic mmu support in EDK2 |
| EDK2_00_09 | CMO support | Rivos | Dhaval Sharma <dhaval@rivosinc.com> | Add support for CMO extension in EDK2 (Need to confirm with Dhaval) |
| EDK2_00_10 | UefiPayloadPkg | Rivos | Dhaval Sharma <dhaval@rivosinc.com> | Add RISC-V support in UefiPayloadPkg (Need to confirm with Dhaval) |
| EDK2_00_11 | EasyDriversDxe | Intel | Andrei Warkentin <andrei.warkentin@intel.com> | Make it easier to develop Tiano drivers, esp. where layered/composite drivers are involved (e.g. device that depends on a PMIC on an I2C bus, a NIC device with a PHY, where the PHY code is easily reusable, auto-binding using DT). May include a source-level compat shim to make it easy to bring U-Boot drivers over to Tiano. |
| EDK2_00_12 | EFI_MP_SERVICES_PROTOCOL | Intel | Andrei Warkentin <andrei.warkentin@intel.com> | At least useful for BRS/HW compliance suite. |
| EDK2_00_13 | libgcc and libatomic libs | Intel | Andrei Warkentin <andrei.warkentin@intel.com> | Similar to ArmPkg/Library/CompilerIntrinsicsLib |
| EDK2_00_14 | DynamicTablesPkg | Intel | Sunil V L <sunilvl@ventanamicro.com> Andrei Warkentin <andrei.warkentin@intel.com> | Prototyped with RiscVVirtPkg? |
| EDK2_00_15 | EDK2 support for separate code and variable storage | Ventana | Sunil V L <sunilvl@ventanamicro.com> | To support secure variables (StandalongMMPkg) and to keep the firmware code as read only, we need to support separate flash images for edk2 code and variable store. QEMU 8.1 enables 2 flash drives for EDK2. So, this is possible only with QEMU 8.1 |
| EDK2_00_16 | Svpbmt support | Ventana | Tuan Phan <tphan@ventanamicro.com> | Add Svpbmt support in EDK2 |
| EDK2_00_17 | Extension Discovery HOB definition | Intel | Andrei Warkentin <andrei.warkentin@intel.com> | PI Spec cleanup and definition of RISCV_CPU_HOB which provides information about few extensions like sstc, cmo and svpbmt used by edk2 |
| EDK2_00_18 | RISC-V QEMU Server Reference Platform | Intel | Evan Chai <evan.chai@intel.com> | Build up a RISC-V server reference platform to address common challenges faced by SOC vendors in developing platform firmware products, thereby minimizing redundant tasks across the board. |
| OpenSBI | ||||
| SBI_00_01 | Sparse HARTID Support | Ventana | Anup Patel <apatel@ventanamicro.com> | Widely needed |
| SBI_00_02 | Firmware-first RAS handling Support | Ventana | ||
| SBI_00_03 | Native/hosted debug support | Ventana | ||
| TF-M | ||||
| TFM_00_01 | TF-M equivalent for secure boot | Imagination Tec | simon.harvey@imgtec.com | |
| U-BOOT | ||||
| UBOOT_00_01 | U-Boot for QEMU PCIe Passthru | Intel | fei2.wu@intel.com | U-Boot needs to handle the memory hole of [3G, 4G), this is a task related to another project: https://wiki.riseproject.dev/display/HOME/SE_01_005+-+QEMU+PCIe+passthru+on+x86+hosts |
| COREBOOT | ||||
| COREBOOT_00_01 | coreboot for SiFive Unmatched | 9elements Samsung | Maximilian Brune of 9elements has an initial port; remaining is to upstream to coreboot. OpenSBI, Linux work correctly, including SMP. All board features work. | |
| COREBOOT_00_02 | coreboot for StarFive VisionFive2 | 9elements Samsung | Port to VisionFive2 | |
| COREBOOT_00_03 | LinuxBoot for coreboot on RISC-V | Samsung 9elements | Verify LinuxBoot operation on 2 or more boards; includes u-root and u-root netboot commands. | |
| COREBOOT_00_04 | TianoCore for coreboot on RISC-V | 9elements | TBD | There is limited interest for now because most LinuxBoot does most of what is needed. |
| MINIMAL SBI Surface for HPC systems | ||||
| HPC_00_01 | Minimal functional SBI definition for HPC | Samsung | rminnich@ssi.samsung.com | HPC scaling requires minimal interface interference from kernel and firmware. This spec is intended to define the minimum viable product for SBI on HPC systems, as well as explore OS-first RAS. |
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