About

This project aims to add the vector cryptographic extensions (0) in QEMU, adding crypto instructions that are aimed on Vector registers.

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Project Scope and Timelines

Changes to related files in target/riscv (for implementation of vector cryptographic extensions) and crypto & include/crypto & target/arm/tcg/crypto_helper.c (for sm4 related part) arounds:

• Refactor some of the generic vector functionality

• Share and reuse some cryptographic implementation (e.g. sm4, aes, etc.)
• Implement the vector cryptographic extensions

Testing with the code samples provided by the vector cryptographic spec repository(ref.).

Components and Repos

Main repo: https://gitlab.com/qemu-project/qemu.git

Pending patch: https://lists.gnu.org/archive/html/qemu-riscv/2023-07/msg00004.html

Stakeholders and Partners

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Dependencies

None

Measure of Success

Patch integrated.

RISE Requirements

None

Misc info

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