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- String and memory functions in libc such as memcpy(), memset(), strcmp(), etc. should run faster with vector optimization than the scalar equivalent (for sufficiently large inputs).
- Implemented code will be tested by RISE member vector testbenches to validate conformance to the RISC-V Vector specification. Contractors will be required to resolve any issues detected by these testbenches.
- Successful proposals should contain a detailed work breakdown (XXX describe the key bits of information needed here)
- Successful proposals should include a test plan describing how the work will be tested before releasing to RISE members for final testing.
- If new TCG ops are required, target implementations should be added to translate to the following host instruction sets:
- x86-64 SSE2
- x86-64 AVX2
- Aarch64 (Advanced SIMD)
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