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The parest benchmark in spec2017 is reasonably friendly for vectorization, performance gains relative to a single FPU scalar implementation should be on the order of 40%35%. Verify the benchmark vectorizes and sees a comparable performance improvement on RISC-V.
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Stakeholders/Partners
RISE:
Ventana: Robin Dapp – lead developer
Ventana: Jeff Law
External:
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Updates
- Currently seeing a 24% decrease in instruction counts when vector is enabled
- Both x86_64 and aarch64 are showing a 35% cycle improvement
- Clearly there is still work to do. It is highly unlikely we're going to hit a 35% performance improvement if we're only seeing a 24% improvement in dynamic instruction vocunts
- Project reported as a priority for 1H2024
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