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The ZiCondops extension provides a conditional zero primitive upon which subsets of conditional move and conditional arithmetic/logical operations can be implemented.   Transforming control flow into conditional operations can improve code performance by eliminating branch mispredict costs as well as reducing the load on the branch predictors.  The earlier in the optimizer pipeline these transformations are performed the more likely they are to expose secondary optimization opportunities as well since the transformations result in larger basic blocks (a fundamental unit of code most compiler optimizations work on).

This work consists of 3 4 subprojects:

1. Basic ZICondops patterns in the RISC-V target description
   1. VRULL + Ventana + ESWIN
2. Improvements to generate those patterns early in the RTL optimizer pipeline
   1. Ventana (primarily Raphael's work with bugfixing from Jeff) + ESWIN
3. Fixes to cost model to enable more conditional move generatinon
4. Improvements to the if-converter to consistently utilize the conditional zero primitive provided by ZICondops
   1. Mixed work from VRULL, Ventana & ESWIN

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Updates

30 Aug 2023 

• Found and fixed missed case affecting CRC loop in coremark
• Still untangling generic changes.  3 significant implementations in play
• Cost model fixes still pending – critically important as we can't add the full suite of tests until that's fixed, hoping to wrap it up this week

09 Aug 2023 

• Target dependent bits to wire up zicond to conditional move support done & integrated
• Improvements to generic code to synthesize conditional arithmetic/logicals under review
  • ESWIN's code looks to be more aggressive in many respects (good)
  • But also less aggressive in handling sub-word cases
  • Not sure yet on approach to be taken
• General upstream agreement that costing model needs work.
• Dependencies on binutils/qemu dropped as they've been resolved.

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