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Updates
- A Spike PR, which implements a Zicfiss v0.3.1 instruction subset, was posted for review by Su-Hsien (MediaTek).
The purpose of the PR is to enable compiler validation and collect feedback. PR: https://github.com/riscv-software-src/riscv-isa-sim/pull/1475 - We have implemented setjmp/longjmp in glibc for Zicfiss. Validation is ongoing. It may require refactoring for upstreaming.
- glibc study to support setjmp/longjmp for Zicfiss is ongoing. It looks that there are many system-related details to consider.
- Update upstream and community activities related to Zicfiss:
- Spike PR for Zimop and Zcmop, which Zicfiss depends on, have been submitted by Ved (Rivos):
https://github.com/riscv-software-src/riscv-isa-sim/pull/1467
https://github.com/riscv-software-src/riscv-isa-sim/pull/1468 - The best place to put the flag for objects compiled with Zicfiss on was discussed by the psABI group. Thank you, Kito (SiFive) and psABI group!
We will implement this in LLVM when the final decision is made.
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/395 - LLVM PR for Zicfiss v0.3.1 is posted by Yeting (SiFive). Thank Yeting again!
https://github.com/llvm/llvm-project/pull/68075
https://github.com/llvm/llvm-project/pull/66043
- Spike PR for Zimop and Zcmop, which Zicfiss depends on, have been submitted by Ved (Rivos):
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