About

The ZiCondops extension provides a conditional zero primitive upon which subsets of conditional move and conditional arithmetic/logical operations can be implemented.   Transforming control flow into conditional operations can improve code performance by eliminating branch mispredict costs as well as reducing the load on the branch predictors.  The earlier in the optimizer pipeline these transformations are performed the more likely they are to expose secondary optimization opportunities as well since the transformations result in larger basic blocks (a fundamental unit of code most compiler optimizations work on).

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Analysis has shown that the most common missed if-conversion cases for RISC-V are related to mode changing operators such as SUBREG, ZERO_EXTEND and SIGN_EXTEND which are commonly used when operating on 32bit objects for rv64..  ESWIN and Ventana have differing implementations in this space that need to be resolved.  The core concern with the ESWIN implementation is that it directly modifies the objects in the IL, which in turn means that it's difficult (potentially impossible) to correctly handle certain cases (shifts).  In contrast the Ventana implementation emits new IL for the converted sequence and deletes the old parts of the IL.

Stakeholders/Partners

RISE:

Ventana: Raphael Zinsly, Jeff Law, Robin Dapp ESWIN: Fei Gao

External:

Dependencies

Status

Updates

23 Jun 2024 

• Remaining items from 1H2024 rolled into new task