Bidding Starts: July 17, 2024
Bidding Ends: August
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13, 2024
Description:
Improvements to compiler codegen is one of the most impactful areas that RISE can help the RISC-V ecosystem. Currently RISC-V compilers need significant improvements relative to other architectures and broad and large gains can be made. RISE is excited to fund a comparison of codegen vs arm64 and use that to drive specific improvements into LLVM.
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RISC-V: LLVM 18.1.6 with rv64gcv_zba_zbb_zbs_zvl256b
name | RISC-V is % worse |
541.leela_r-0 | 39.47% |
531.deepsjeng_r-0 | 36.41% |
525.x264_r-0 | 34.24% |
525.x264_r-1 | 28.73% |
525.x264_r-2 | 27.38% |
526.blender_r-0 | 25.08% |
508.namd_r-0 | 24.83% |
544.nab_r-0 | 24.33% |
538.imagick_r-0 | 19.39% |
511.povray_r-0 | 17.56% |
500.perlbench_r-2 | 14.56% |
Analyze the SPEC benchmarks for performance issues, and where possible bring LLVM to parity with AArch64. We prefer for the time being to use dynamic instruction count despite understanding its flaws as a metric because we want a vendor-neutral metric. Additionally, the gaps are so large vs AArch64 at this point that we are unlikely to overfit to this metric. That said, we expect engineers to use judgment and avoid intentionally overfitting should that arise during work.
Please identify what milestones RISE can expect to be accomplished within a budget of US$250,000 .
The Phase 2 of this Project will be a separate effort that will be informed by the results of Phase 1.
For questions regarding this RFP please email info@riseproject.dev
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