...
Add HWPROBE based discovery for various ZvlZv* sub- extensions which define supported vector lengthsare not implied by V-extension:
Zvl32b
Zvl64b
Zvl128b
Zvl256b
Zvl512b
Zvl1024b
The V-extension implies following features so these does not require separate discovery:
Zvl128b
EEW of 8, 16, and 32, and 64
Vector configuration instructions (vsetvli/vsetivli/vsetvl)
Vector load and store instructions
Vector integer instructions
Vector fixed-point arithmetic instructions
Vector integer single-width and widening reduction operations
Vector mask instructions
Vector permutation instructions
Refer, Chapter18 of https://github.com/riscv/riscv-v-spec/releases/tag/v1.0
Status
Page Properties | |||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Timeline | Q3 2023 Contacts | Unassigned
|
Updates
Project reported as priority for 2H23
Nothing required to be done for this item because user-space can discover supported vector length from CSR WARL fields.