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We recently discussed this optimization with the wider LLVM RISC-V community. The takeaway was this work probably should be done in the generic optimizer rather than in a RISC-V specific pass.
RFC for Joe's implementation and merge request.
Stakeholders/Partners
RISE:
Imagination Technologies: Joe Faulls
Ventana: Mikhail Gudim
Ventana: Jeff Law
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Updates
- Moved to 2H2024
- Last update to MR was late April. Unsure of status
- Joe Faulls (Imagination Technologies) seems to have picked up this work, which is greatly appreciated. Links to the discussion and MR provided above.
- After generally positive reception in RISC-V LLVM coordination meeting, Misha is looking to generalize the implementation so that it fits into the regular LLVM optimization pipeline
- Review of relevant documentation and GCC's implementation for validation that a given loop is computing a CRC (linear feedback shift register)
- Project reported as priority for 1H2024
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