• About
• Project Scope and Timelines
• Components and Repos
• Stakeholders and Partners
• Dependencies
• Measure of Success
• RISE Requirements
• Status

About

Implement the RISC-V Server SoC/Platform Reference Board (Similar to ARM sbsa-ref board).

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Reference 2: https://github.com/riscv-non-isa/riscv-server-platform

Project Scope and Timelines

The project will take place during 2024. The major milestones:

1. Stage 1: A basic framework that can boot upstream linux and run the BRS tests.
2. Stage 2: A detailed SoC model that support most Server SoC/Platform Spec (IOMMU, PCIe)
3. Stage 3: A full-fledge SoC model that complies with the Server SoC/Platform Spec (RVA23 profile, RAS, QoS etc), and passes the Server SoC Testsuite (https://github.com/riscv-non-isa/server-soc-ts/)

Components and Repos

Upstream Qemu.

Stakeholders and Partners

Other QEMU for RISC-V contributors, including:

• Intel/RISE
  
  • Wu Fei
  • Andrei Warkentin - RISC-V Server Platform
• RIVOS/RVI
  • Ved Ved Shanbhogue – RISC-V Server SoC TG Chair
•  Alibaba/RVI
  • Shaolin Xie – RISC-V Server SoC TG Vice-Chair
  • Zhudie Chen

Dependencies

1. We may need the upstreamed RISC-V IOMMU model in Qemu
2. We need the corresponding FW/UEFI package to boot linux.

Measure of Success

An accepted and tested design and implementation in 2024.

1. The Qemu/FW packages pass the RISC-V Boot and Runtime Services (BRS) Testsuite: https://github.com/intel/rv-brs-test-suite

RISE Requirements

(not accounting any of existing engineering investment against RISE resources).

1. We need to create a repo in RISE to hold the development code.

Status

Updates

12 Mar 2024 

v2: https://www.mail-archive.com/qemu-devel@nongnu.org/msg1030456.html

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