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Ventana: Jeff Law – oversight, patch review
External:
Significant design work and theoretical background provided by Philipp Tomsich and Henry Brausen of VRULL
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Updates
- Mariam has posted the CRC optimization work for upstream review. This includes methods to generate CRC using clmul, table lookups for RISC-V. For testing purposes it also supports AArch64 and x86_64's clmul variants as well as the x86_64 crc instruction if the proper polynomial is used.
- Jeff Law has started review work. Expecting to get input from Intel and ARM/Linaro engineers as the implementation includes support for those architectures.
- Simple tests using this code to detect a CRC loop that is compatible with the x86 crc32 instruction and generating the crc32 instruction for such loops show using the crc32 instruction is at least 5X faster than a loop.
- Currently investigating generating aarch64 clmul as there is a bit time to do this as a proof of concept before focusing on the upstreaming effort.
- It had been speculated that this work could generate a "crc" instruction on suitable ISAs if a loop with the right field polynomial were encountered. This has been implemented as a proof of concept on x86
- It has also been speculated that this work could be used to detect clmul idioms outside of a CRC loop. This appears to work by relaxing various aspects of the CRC loop verifier. It is not an area of focus though.
- Minor bugs have been fixed in the implementation as it is prepared for upstreaming. Goal is still integration for gcc-15 in the late spring.
- Implementation done for x86_64 using its clmul. Primary purpose was to show that using clmul, while requiring target specific development, is not a major effort. This is expected to help with the upstreaming effort.
- Code drop from 1/26 integrated into the upstream GCC tester.
- Expectation is to submit code for upstream review in Feb with a goal of integrating for gcc-15 in the late spring.
- Major cleanups/fixes have been made in the gimple→RTL code generation phase. At this point CRC detection and code generation using table lookups is expected to work on any architecture GCC supports. Additionally generation of clmul instructions is supported on RISC-V when the appropriate extension is enabled.
- At this point the development cycle is considered complete and we will be working through the usptreaming process with a target of inclusion in gcc-15 (spring 2025)
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