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However, there are several cases where the compiler can know it is safe to avoid the extension.  For example for (1 << N), if we know N can never have the value 31, then we know bit 31 will not be modified and thus no explicit extension is needed.We have also seen cases where we have multiple variable bit manipulation instructions modifying the same bit.  For example a bclr followed by a bset.  This happens in perlbench's bit manipulation routines for example.  WIth a bit of work the redundant bit operation can be removed.

GCC will sometimes generate unexpected RTL for setting/clearing a bit.  Usually these are represented as logical operations; however, in some cases than can be represented as a bit extract/deposit (zero_extract in GCC's terminology).  These show up in the GCC benchmark within spec.  Patterns for these cases should be added to the compiler.

For an explicit zero-extension from of 1 << N from 32 to 64 bits, we can generate bset directly.  We know this will never set bits 32..63 and thus it is already zero-extended.

To invert the result of a bext, we can use bext+seqz. 

1. xalancbmk's bitset implementation has a redundant bit clear before setting the same bit.  This can be fixed in a generic way with an additional logical simplification pattern 
2. bext can be used to extract a single bit, storing the result into an SImode object, even for rv64 since bits 1..63 will be zero'd by the (&1) operation in the bext specification.
3. ~(1 << N) & C can be safely used for a 32bit object on rv64 when C has 33 or more leading zeros
4. (1 << N) | C and (1 << N) ^ C can be safely used when the logical XOR/IOR is done in DImode since we don't have to worry about sign-extending a DImode object
5. An explicit extension of SImode (1 << N) to DImode can be handled with a simple bset with x0 as a source operand
6. Occasionally GCC will use a "zero_extract" as a destination for some bifield insertions which can be handled with bset/bclr
7. When the shift count is masked such that we know bit 31 is not changed we can more aggressively generate Zbs instructions.  Two forms
   1. Bit position is masked via AND.
   2. Bit position is masked via NAND

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Updates

06 Jul 2024

• Last patch in series committed  (exploiting masks of count). 

19 Jun 2024 

• Generalization of IOR patterns to include XOR submitted.
• Wrapped up new version of patch to exploit masking of bit position.
• Marking as development complete.

17 Jun 2024

• (1 <<N) | C and (1 << N) ^ C for DImode objects has been integrated
• Explicit zero extension of (1 << N) in SImode  using bset has been submitted & integrated
• Handling of zero_extract destinations for single bit insertions has been submitted & integrated

10 Jun 2024 

• Raphael's code for using bext to extract a single bit, storing the result in an SImode object for rv64 has been integrated
• Raphael's code to handle ~(1 << N) & C where C has at least 33 leading zeros has been integrated
• Jeff's code to handle (1 << N) | C and (1 << N) ^ C for DImode objects has been submitted

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