About
The ZiCondops extension provides a conditional zero primitive upon which subsets of conditional move and conditional arithmetic/logical operations can be implemented. Transforming control flow into conditional operations can improve code performance by eliminating branch mispredict costs as well as reducing the load on the branch predictors. The earlier in the optimizer pipeline these transformations are performed the more likely they are to expose secondary optimization opportunities as well since the transformations result in larger basic blocks (a fundamental unit of code most compiler optimizations work on).
This work consists of 3 subprojects:
- Basic ZICondops patterns in the RISC-V target description
- VRULL + Ventana + ESWIN
- Improvements to generate those patterns early in the RTL optimizer pipeline
- Ventana (primarily Raphael's work with bugfixing from Jeff) + ESWIN
- Improvements to the if-converter to consistently utilize the conditional zero primitive provided by ZICondops
- Mixed work from VRULL, Ventana & ESWIN
Evaluation of the initial implementation has indicated that idioms to implement 32 bit operations on rv64 are consistently not if-converted. Improvements to capture those cases are in progress.
Stakeholders/Partners
RISE:
Ventana: 1 FTE (Christoph Muellner and Philipp Tomsich) for initial development
Ventana: 1 FTE, ~12 wks. Raphael Zinsly. Revamped basic support in preparation for upstreaming, support for conditional 32bit ops, conditional move support early in the compiler optimization pipeline
Ventana: Jeff Law. Integration of Raphael's work with upcoming changes from Philipp.
Rivos: Oversight & review.
SiFive: Oversight
External:
VRULL: Philipp Tomsich. Initial work under contract to Rivos and Ventana. Ongoing updates
ESWIN: Submission of basic Zicond support, conditional move and limited improvements to ifcvt
Dependencies
Status
Updates
- Target dependent bits to wire up zicond to conditional move support done & integrated
- Improvements to generic code to synthesize conditional arithmetic/logicals under review
- ESWIN's code looks to be more aggressive in many respects (good)
- But also less aggressive in handling sub-word cases
- Not sure yet on approach to be taken
- General upstream agreement that costing model needs work.
- Dependencies on binutils/qemu dropped as they've been resolved.
- Several bugs found & fixed in additional optimization patterns provided by ESWIN
- Costing model issues are deeper than anticipated. May spin out distinct project for that
- Initial bits to wire up zicond to implement conditional moves ready to land
- Basic Zicond support from ESWIN is the same as Ventana's internal bits and in-line with where VRULL was asked to go
- Basic support integrated
- Working on costing model which we ought to have sorted out 7/26.
- Next will be unifying the ESWIN and Ventana bits to enable limited conditional move support using Zicond
- After that we need to evaluate what if-converter bits are needed.
- Slow movement here has resulted in a "competing" implementation.
- Manolis from VRULL has started posting some of the generic work to facilitate use of Zicond/Xventanacondops
- Jeff from Ventana continues to fix bugs in code which exposes Zicond/Xventanacondops to tree→RTL expansion code (internal to Ventana right now, but definitely planned to upstream)
- Binutils dependency has been resolved (Zicondops will appear in binutils-2.41 in July)
- VRULL will repost their work. Ventana will coordinate with VRULL on review/updates
- Note QEMU dependency
- Consistent reporting of stakeholders/partners
- ZICondops binutils patch (re)approved
– Dates on or before June 15 are approximate
- Project reported as priority for 2H23