These are two tasks carried forward from 1H2024 and some additional work identified in 2024
Jivan has a small patch which detects generation of some redundant sign/zero extensions in the RISC-V backend. This is not expected to produce any significant benchmark improvements, but mostly serves as a final catch for corner cases so that we don't have to debug them again. To date cases detected have all been due to expansion of builtins which perform overflow checking of basic integer operations.
To date this has only triggered as a result of the expansion of arithmetic with overflow checking
Probably still worth integrating
Eliminate the redundant sign extension after an inlined strcmp.
Eliminate the redundant sign extension after an inlined memcmp
sCC code generation will often need mixed modes and would benefit from Jivan's trick
Stakeholders/Partners
RISE:
Ventana: Jeff Law
Rivos: Vineet (part time)
External:
Dependencies
Status
Development
Development Timeline
2H2024
Upstreaming
Upstream Version
gcc-15
Spring 2025
Contacts
Jeff Law (Ventana)
Dependencies
None
Updates
Incomplete/New items moved to 2025.
Jivan's patch to avoid zero/sign extending a value already known to be appropriately extended has been integrated.
Note that sCC expansion code can benefit from Jivan's trick as well and a patch implementing that has been integrated.
Elimination of the redundant extension after inlined strcmp and memcmp are upstreamed.