SE_01_023 - QEMU RISC-V IOMMU enhancements

 

About

This is a follow up of the RISC-V IOMMU work after the base support was accepted upstream in QEMU.

The following features will be implemented:

  • HPM (Hardware Performance Monitor: this feature was split from the base support before merging it

  • riscv-iommu-sys platform device

  • MSI support for the riscv-iommu-sys platform device

  • Integrate the riscv-iommu-sys platform device in the ‘virt’ machine

Project Scope and Timelines

The project will take place during 2025.

Components and Repos

Upstream Qemu.

Stakeholders and Partners

Other QEMU for RISC-V contributors, including:

  • RISE

    • @Daniel Barboza

  • External

    • Alistair Francis (QEMU for RISC-V maintainer)

Dependencies

No dependencies.

Measure of Success

An accepted and tested design and implementation in 2025.

RISE Requirements

None (not accounting any of existing engineering investment against RISE resources).

Status

Development

Completed

 

Development Timeline

1H2025

 

Dependencies

None

 

Upstreaming

Not Started

 

Upstream version

QEMU 10.0

 

Contacts

@Daniel Barboza