This is an ongoing activity carries over from prior semesters: Please refer to 2024-2H and 2025-1H for background.

Cactu spills are coming from sched1 not reducing live range. Continue working on PR/114729 (partially addressed in gcc-15, more work to be done in this semester.

Paul-Antoine has noted redundant addi instructions PR/120811 that should have folded into a memory reference. This is an unintended consequence of Vineet's fix misinteracting with mvconst_internal spiltter and is likely solveable by rewriting the addsi/addi expanders, then creating an add_ptr3 pattern that uses the same infrastructure

Doesn't directly solve the problem, but should set things up so that fold-mem-offsets can clean things up - this would reduce the cost of spill

Can we improve post-reload optimizers to help (assuming there's still notable amounts of code to fix)

Christophe has a major revamp of fold-mem-offsets which may help further

Can reload_cse help at least with removal of the totally redundant computations?

What about move2add? Or is it getting neutered by hard register reuse?

Stakeholders/Partners

RISE:

Rivos: Vineet Gupta

Ventana: Jeff Law – general oversight / guidance, testing, regression fixing, etc.

External:

Dependencies

Status

Development	IN PROGRESS
Development Timeline	1H2025
Upstreaming	IN PROGRESS
Upstream Version	gcc-16 (target) (Spring 2026) Bullet list
Contacts	Vineet Gupta (Rivos) Jeff Law (Ventana)
Dependencies	None

Updates

Jul 16, 2025

Vineet's work dramatically reduced the number of scalar instructions, particularly those related to address computations. I've forgotten the details, but it was a measurable improvement on Ventana's Veyron V2 design.
Paul-Antione has found some other scalar codegen issues PR/120811 that are being addressed under the wider space of mvconst_internal removal