About

RISC-V Vector (RVV) provides vector segment load/store instructions that efficiently handle interleaved memory layouts and can replace gather/scatter generated by the loop vectorizer.

Goals:

1. Enable tail-folding for loops with interleaved groups by using masked segment loads/stores, avoiding fallback to indexed (gather/scatter) accesses.

2. Lower masked segment loads/stores to unmasked segment loads/stores with an explicit vector length (EVL).

Update:

[Landed] Enable masked interleave access #151665https://github.com/llvm/llvm-project/pull/151665

[Landed] Support interleaved access with tail folding by EVL #152070https://github.com/llvm/llvm-project/pull/152070

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Status

Updates

Oct 2, 2025

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