Project RP008_Toolchain - GCC SPEC2017 Optimization
- Michelle Martineau
- Evan Harrison
- Barna A Ibrahim
Bidding Starts: Wednesday, May 16 , 2024
Bidding Ends: Wednesday, May 29 , 2024
Contract start date: TBD
Summary:
Improvements to compiler codegen is one of the most impactful areas that RISE can help the RISC-V ecosystem. Currently RISC-V compilers need significant improvements relative to other architectures and broad and large gains can be made. RISE is excited to fund a comparison of codegen vs arm64 and use that to drive specific improvements into GCC.
Milestones to Deliver:
Phase 1: Analysis and improvements of SPEC
- Codegen improvements in GCC. The company should focus on all or a subset of SPEC 2017. Identify and fix weaknesses to bring RISC-V codegen up to parity with or if possible exceed Aarch64. Larger items identified can be documented (with a code and assembly snippet) without being fixed, at the discretion of the contracting company.
- Architectural deficiencies in RISC-V. Identify cases which are primarily driven by differences in the ISA. For example, AArch64 performing better because it has a richer set of addressing modes for vector instructions and similar kinds of issues. Ideally this section would identify the component of spec2017 that is affected, show a C/C++/Fortran code fragment for the problem and the corresponding AArch64 and RISC-V assembly for the fragment.
Here is the Analysis RISE has done.
- RISC-V GCC trails arm64 GCC and RISC-V LLVM on a subset of the SPEC 2017 benchmarks. When measuring dynamic instruction counts, some of the larger outliers are:
benchmark | workload # | vs. SVE2 |
549.fotonik3d_r | 0 | -79.90% |
554.roms_r | 0 | -73.13% |
525.x264_r | 1 | -62.26% |
525.x264_r | 2 | -58.84% |
503.bwaves_r | 1 | -40.41% |
503.bwaves_r | 3 | -40.05% |
503.bwaves_r | 0 | -39.84% |
503.bwaves_r | 2 | -39.67% |
525.x264_r | 0 | -38.91% |
521.wrf_r | 0 | -36.46% |
510.parest_r | 0 | -26.03% |
526.blender_r | 0 | -17.53% |
541.leela_r | 0 | -13.73% |
508.namd_r | 0 | -12.32% |
511.povray_r | 0 | -11.58% |
502.gcc_r | 4 | -10.52% |
- We have some known issues, including:
- Missing register+register addressing patterns
- Email info@riseproject.dev to if you would like to see additional analysis RISE team has done.
- Analyze the SPEC benchmarks for performance issues, and where possible bring GCC to parity with arm64. We prefer for the time being to use dynamic instruction count despite understanding its flaws as a metric because we want a vendor-neutral metric. Additionally, the gaps are so large vs arm64 at this point that we are unlikely to overfit to this metric. That said, we expect engineers to use judgment and avoid intentionally overfitting should that arise during work.
- Please identify what milestones RISE can expect to be accomplished within a budget of US$200,000 .
The Phase 2 of this Project will be a separated RFP in 2H2024 on additional SPEC benchmark improvements.