Topic ID	Topic Name	Priority	Development	Upstreaming	Dependency	Tentative ETA	Company	Contact	Comments
Valgrind (00)
DP_00_001	Valgrind vector support	Unknown	InProgress	InProgress		Q4 2023	Intel	fei2.wu@intel.com	1. RV on Valgrind w/o Vector: https://github.com/petrpavlu/valgrind-riscv64 2. this task to support RVV framework + selected instructions on valgrind
DP_00_002	Valgrind(mainly focus on the vector instruction support)	Medium	InProgress	Unknown		?	T-Head	yunhai.syh@alibaba-inc.com	helper function based RVV implementation: https://github.com/rjiejie/valgrind-riscv64
DP_00_003	Valgrind	Low	Unknown	Unknown		Q3 2023	Ventana	jlaw@ventanamicro.com	Basic rv64 functionality to run Linux binaries correctly. Then support for the extensions in RVA22/RVA23.
DP_00_004	Valgrind bitmanip, V, Zvk, etc. support	Medium	Unknown	Unknown		2024	SiFive/Intel/CAS		Better to break down the task into B-ext/V-ext/Zvk subtasks, so we can co-ordinate the effort.
DP_00_005	Valgrind scalable vector IR	Medium	Unknown	Unknown		2024	Intel	xiao.w.wang@intel.com	To introduce a unified scalable vector IR design to accommodate both ARM SVE and RISCV RVV
DP_00_006	Support mulhsu insn	Medium	Completed	InProgress		2024	Intel	xiao.w.wang@intel.com	https://github.com/petrpavlu/valgrind-riscv64/pull/22
DP_00_007	Support all "csr*i" insns	Medium	Completed	InProgress		2024	Intel	xiao.w.wang@intel.com	https://github.com/petrpavlu/valgrind-riscv64/pull/22
DP_00_008	Support fence.i	Medium	InProgress	Unknown		2024	Intel	xiao.w.wang@intel.com
GDB (01)
DP_01_001	GDB	Low	InProgress	Unknown		Q1 2024	BOSC	zhangjian@bosc.ac.cn	Hardware Watchpoints,Inferior function calls
DP_01_002	Evaluate GDB status on RISC-V	Medium	Unknown	Unknown			Andes	hellosun@andestech.com	https://lf-rise.atlassian.net/wiki/pages/viewpage.action?pageId=8585968
DP_01_003	Add Zc support to GDB Simulator	Medium	InProgress	NotStarted		Q3 2023	Imagination	simon.harvey@imgtec.com	https://lf-rise.atlassian.net/wiki/display/HOME/DP_01_003+-+GDB+Simulator+-+Add+Zc+support
DP_01_004	Add native Linux support for dump vector register content	Medium	InProgress	InProgress			SiFive	carsten.gosvig@sifive.com	`info vector` works for remote GDB but not when running natively
DP_01_005	Add support for vector and scalar _Float16 type	Medium	Unknown	Unknown			SiFive	carsten.gosvig@sifive.com	https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/main/doc/rvv-intrinsic-spec.adoc#floating-point-types
DP_01_006	Add support for vector and scalar __bf16 type	Medium	Unknown	Unknown			SiFive	carsten.gosvig@sifive.com	https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/main/auto-generated/bfloat16/intrinsic_funcs.adoc
DP_01_007	Add support for landing pads	High	Unknown	Unknown			SiFive	carsten.gosvig@sifive.com	GDB must not set SW breakpoint on `lpad` instruction, but on the next instruction
DP_01_008	Add support for shadow stack	Unknown	Unknown	Unknown			SiFive	carsten.gosvig@sifive.com	GDB should support inspection&modification of the shadow stack
DP_01_009	Add support for pointer masking	Unknown	Unknown	Unknown			SiFive	carsten.gosvig@sifive.com	GDB needs to unmask addresses that are still masked before using
LLDB (02)
DP_02_001	LLDB for RV64	Low	Unknown	Unknown			SiFive	https://reviews.llvm.org/D62732	https://reviews.llvm.org/D62732
DP_02_002	Evaluate LLDB status on RISC-V	Medium	Unknown	Unknown			Andes	hellosun@andestech.com	https://lf-rise.atlassian.net/wiki/pages/viewpage.action?pageId=8585968
DP_02_003	Support coredumps for RV64	Medium	Completed	Completed			Samsung	alexey.merzlyakov@samsung.com	https://github.com/llvm/llvm-project/pull/93297
DP_02_004	FPR to be enabled/disabled	Low	Completed	Completed			Samsung	alexey.merzlyakov@samsung.com	For non-FP setups, like RV64IMAC, we need to have optionally disabled FPR on them https://github.com/llvm/llvm-project/pull/104547
gprofng (03)
DP_03_001	gprof-ng	Low	Unknown	Unknown		Q4 2023	Ventana	jlaw@ventanamicro.com	Basic support for RV, particularly as it moves into the datacenter. Probably not that important on the embedded side.
Perf (04)
DP_04_001	Userspace Cycle/Instret access	High	Completed	Completed		Q3 2023	Rivos	Alexandre Ghiti <alexghiti@rivosinc.com>
DP_04_002	Perf event discovery/encoding from json file	Medium	Done	NotStarted		Q1 2024	Rivos	atishp@rivosinc.com
DP_04_003	Perf CTR (equivalent of x86 LBR) support	Medium	Done	NotStarted		Q1 2024	Rivos, SiFive	atishp@rivosinc.com, eric.lin@sifive.com
DP_04_004	Perf CTR call stack mode support	Medium	Unknown	Unknown		Q1 2024	Rivos, SiFive	atishp@rivosinc.com, eric.lin@sifive.com
Sanitizer (05)
DP_05_001	Address sanitizer	High	Completed	InProgress		2024	T-Head	yunhai.syh@alibaba-inc.com	support RV32I in LLVM and GCC, research on optimization cooperate with Memory tagging extension
ToolChain (06)
DP_06_001	riscv-gnu-toolchain	Unknown	Unknown	Unknown			SiFive	kito.cheng@sifive.com
DP_06_002	binutils	Unknown	Unknown	Unknown			SiFive	kito.cheng@sifive.com
DP_06_003	ILP32 PSABI	Medium	InProgress	Unknown		2024	SiFive	kito.cheng@sifive.com	PLCT guys has init implmenation, but need more survey for other ilp32 ABI like x32, ilp32/aarch64 and MIPS n32
DP_06_004	DWARF representation for RVV	Unknown	Unknown	Unknown			Red Hat
DynamoRIO (07)
DP_07_001	DynamoRIO initial support	Medium	InProgress	Completed		2024	Rivos	adlr@rivosinc.com	We kicked off the inital work and posted it upstream, but haven't been able to continue it
DP_07_002	DynamoRIO basic support	Medium	Completed	Completed		H2 2023	ISCAS	liuyang22@iscas.ac.cn	Core module is now partially usable, part of the clients are also working. All of the work has been upstreamed. https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/621mLGYsYz0?pli=1
DP_07_003	DynamoRIO drcachesim & drcov support	High	InProgress	InProgress		H2 2024	ISCAS	liuyang22@iscas.ac.cn
DP_07_004	DynamoRIO V extension support	High	InProgress	InProgress		H2 2024	ISCAS	liuyang22@iscas.ac.cn
DP_07_005	DynamoRIO enable remaining tests that are also supported by AArch64	Medium	InProgress	InProgress		H2 2024	ISCAS	liuyang22@iscas.ac.cn
DP_07_006	DynamoRIO RISC-V specific documentation	Medium	NotStarted	NotStarted		H2 2024	ISCAS	liuyang22@iscas.ac.cn
OpenLink (08)
DP_08_001	openLink unifed debug probe protocol and firmware	Medium	Completed	NotStarted		2024	T-Head	yunhai.syh@alibaba-inc.com
eBPF (09)
DP_09_001	Evaluate status on RV: bpftrace	Medium	Completed	Completed		2024	T-Head	cp0613@linux.alibaba.com	https://github.com/iovisor/bpftrace The mainline already supports RV, we are already using it, please pay attention to enable kernel CONFIG.
DP_09_002	Evaluate status on RV: bcc	Medium	Completed	Completed		2024	T-Head	cp0613@linux.alibaba.com	https://github.com/iovisor/bcc The mainline already supports RV, we are already using it, please pay attention to enable kernel CONFIG.
DP_09_003	Evaluate status on RV: cilium	Unknown	Unknown	Unknown
DP_09_004	Evaluate status on RV: bpftune	Unknown	Unknown	Unknown
DP_09_005	bpf JIT optimization based on Zba extension	Medium	Completed	Completed		2H 2024	Intel	xiao.w.wang@intel.com	patches are merged into mainline kernel.
Performance Benchmarking and Analysis (10)
DP_10_001	LKP framework enablement on RISC-V	High	InProgress	InProgress		2H2023	Intel	xiao.w.wang@intel.com	https://github.com/intel/lkp-tests.git, build robot for riscv is already working
DP_10_002	LKP workload enablement on RISCV-V	Medium	Unknown	Unknown			Intel	xiao.w.wang@intel.com
DP_10_003	Build performance CI infrastructure	Medium	Unknown	Unknown			Intel	xiao.w.wang@intel.com
Simpleperf
DP_11_001	Simpleperf (primarily used on Android)	High	Unknown	Unknown		1H2024	SiFive	kevin.mills@sifive.com
OpenOCD
DP_12_001	Evaluate OpenOCD status on RISC-V	Unknown	Unknown	Unknown			Andes	hellosun@andestech.com	https://lf-rise.atlassian.net/wiki/pages/viewpage.action?pageId=8585968

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