About

The WRF benchmark in spec2017 is fairly sensitive to the performance of the atan2f function in glibc.  A better performing implementation of atan2f is possible on designs which have dual FP units and a reciprocal estimator in the vector unit.

Specifically we want to convert the IA-64 assembly implementation into a series of __builtin_XYZ calls to generate the reciprocal estimation and a series of fmas.   The RISC-V ISA does not have a reciprocal estimator in the FP unit, instead it's implemented in the vector unit with 7 bits of accuracy.  So we'll need to do the estimation step in the vector unit and bring the result over to the FP unit which adds additional overhead.  The computation steps have a reasonable degree of parallelism and with dual FMAC units should be able to out perform the generic implementation in glibc.

I have implemented this exact procedure in the past on a private port, so I know it was viable and produced a nice performance gain (double digits).  The gain on RISC-V will likely be smaller as we have additional overhead to get the estimate out of the vector unit and need an additional iteration to deal with accuracy limitations of the reciprocal estimation algorithm.   So clearly this will need benchmarking on real hardware (or at least cycle approximate simulators). 

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Status

Updates

Jun 5, 2024 

• Move to 2H2024 given we haven't got good data on the performance concerns with getting the recip estimate out of the VPU into the FPU

Dec 29, 2023 

• Project reported as a priority for 1H2024