Background

Based on the ongoing discussions in the Systems' Libraries WG, there are gaps that have been identified in the RISC-V Vector 1.0 specification for . A few different proposals are being proposed to close the gap, e.g., Rivos zip/unzip, Bytedance vtrn, vabd, etc.

As the proposals are being discussed, there is interest in evaluating the instructions through the path of implementations (whether its GEM5, FPGA, RTL or something else). In order to align the two sides - requirements providers / user and the implementors, let’s summarise the instructions, their behaviour and potential encodings.

Proposal Summary