About
This project aims to add the vector cryptographic extensions (0) in QEMU, adding crypto instructions that are aimed on Vector registers.
Adding this support will allow QEMU to be used as a hardware replacement for cryptographic development when hardware access with vector crypto support is not available.
(0) https://github.com/riscv/riscv-crypto/releases
Project Scope and Timelines
Components and Repos
Stakeholders and Partners
Dependencies
None
Measure of Success
RISE Requirements
None
Misc info
The development was made by SiFive in collaboration with CodeThink.