Bidding Starts: Friday, December 18, 2023

Bidding Ends: Friday, February 2, 2024

Proposal:

Implement translation of RISC-V Vector and Vector Crypto instructions to TCG ops. The goal of this proposal is to optimize execution of RISC-V binaries under QEMU that make heavy use of the V (vector) and Zvk (vector crypto) extensions so that they perform sufficiently fast enough that QEMU is a viable emulation platform for development. To do this, these instructions should be mapped to the closest equivalent hardware on the host, taking full advantage of full SIMD vector lengths (up to 256 bit on AVX2) to maximize throughput. Only ratified RISC-V Vector extensions (vector-1.0 and vector-crypto-1.0.0) are targeted in this project.

Milestones to Deliver:

This is a proposed work breakdown; contractors may propose an alternate work breakdown)

Minimal Requirements:

String and memory functions in libc such as memcpy(), memset(), strcmp(), etc. should run faster with vector optimization than the scalar equivalent (for sufficiently large inputs).
Implemented code will be tested by RISE member vector testbenches to validate conformance to the RISC-V Vector specification. Contractors will be required to resolve any issues detected by these testbenches.
Successful proposals should contain a detailed work breakdown (XXX describe the key bits of information needed here)
Successful proposals should include a test plan describing how the work will be tested before releasing to RISE members for final testing.
If new TCG ops are required, target implementations should be added to translate to the following host instruction sets: