About

Currently, only RISC-V INTC interrupt controller is supported in QEMU ACPI virt machine. Add AIA interrupt controllers (IMSIC, APLIC) so that IO devices can be used with ACPI.

Project Scope and Timelines

Changes to hw/riscv/virt.c and hw/riscv/virt-acpi-build.c around:

Migrate few common functions from hw/arm/virt-acpi-build.c to a common location so that RISC-V can use the same.
Update RINTC structure to support IMSIC and APLIC
Add IMSIC in MADT
Add APLIC in MADT
Add perfipherals in DSDT (UART, PCI, virtio)

In addition, add CMO and MMU nodes in RHCT.

Components and Repos

Upstream Qemu.

Stakeholders and Partners

Other hw/riscv/virt.c contributors, including:

RISE
- Andrei Warkentin, Daniel Henrique Barboza
External
- Alistair Francis

Dependencies

None.

Measure of Success

An accepted and tested design and implementation by end of 2H23 (slated for merging).

RISE Requirements

None (not accounting any of existing engineering investment against RISE resources).

Status

The table below is rolled up to the Simulator WG status page Simulator/Emulator 2023 Projects .

Development	COMPLETED
Development Timeline	2H23
Dependencies	None
Upstreaming	COMPLETED
Upstream Version		9.0
Contacts	Sunil V L

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