RISE TSC Meeting Notes
March 20, 2025
Security Software WG Deep-Dive: Robin Randhawa
Timeline of Events (or the story thus far)
This is the first Security SW WG Deep Dive to the RISE TSC
This is a relatively new Working Group
Justification for the WG first pitched to the RISE TSC in June 2024
Generally unanimous support
Working Group created in August 2024
First WG Kick-off meeting in September 2024
Monthly meets since then
The story arc that has evolved since the WG’s inception
Initially: “Security is broad: What is it that we want to do ?”
Then: “Let’s look at all the security specific RVIA specs that are frozen/ratified”
Then: “Let’s focus on security for embedded first! No! Datacenter/enterprise first!”
Then: “Let’s find a common feature subset between embedded and the rest”
Then: “Let’s focus on embedded first but choose work that enables the rest too”
Finally: “Here’s a break-down of the work we need to do first, let’s talk”
Current Status: OP-TEE for RISC-V Work Definition in Progress
Next Steps
Complete OP-TEE/OpenSBI work definitions
Get reviews done by key stakeholders (Firmware/SecSW WGs)
Post review - translate to RISE WG work packages
Nominate work package owners
Produce RFPs for suitable work to rope in contractors
Bring in focus beyond embedded
Undergo a similar consensus driven work identification exercise
Areas
CoVE enablement
Qemu, OpenSBI, CoVE RDSM
Build work package definitions, get them reviewed
Nominate owners, produce RFPs
What has worked well
Good, gradual convergence of opinions towards common goals
Good cross WG collaboration!
Credits
Anup Patel (VentanaMicro)
Sunil VL (VentanaMicro)
Tim Ouyang (AndesTech)
Alvin Chang (AndesTech)
Ravi Sahita (Rivos)
Peter Lin (SiFive)
What has not worked well
Everyone is busy!
Hard to get timely responses generally speaking
Need to constantly push and prod folks…
More mailing list interactions needed
General tendency to leave discussions until WG monthly meets
Will try hard to change this!
More enthusiasm needed!
Not enough folks attending monthly WG meets
Security is a generally dry topic, yes, but it is super important!!!
Mar 13, 2025
RISE Developer Infrastructure Deep Dive- Paul Walmsley
Topics
Developer Infrastructure WG Introduction & Vision
Build Farm
Introduction
Value
2024Q4 Review
2025Q1 Review
Board Farm
Developer Tools
Looking Forward to 2025Q2
Credits
Developer Infrastructure WG Introduction
Charter
The Developer Infrastructure WG focuses on software and services to support open-source RISC-V developers - both RISE members and the broader open-source community.
Co-chairs
Barna Ibrahim (Rivos)
Paul Walmsley (SiFive)
TSC Chair Contact
Nathan Egge (Google)
Developer Infrastructure WG Vision
Three mutually-supporting projects
RISE Build Farm (Active)
RISE Board Farm (Inactive)
RISE Developer Tooling (Active)
Goal
Provide robust development infrastructure and tools to RISC-V developers
RISE Build Farm: Introduction
Objective
Cross-build and test (in simulation) RISC-V ports of key open source software
Running in Hetzner Cloud (new!)
Björn Töpel (Rivos) coordinating
Brian “Redbeard” Harrington (Red Hat): co-admin
Status
Eight active projects
~22 active large VM instances on Hetzner Cloud
Mostly acting as Github Runner performing cross-compilation/qemu-system-riscv{32,64} tests
Build Farm: Value
Thousands of builds, and millions of tests per month on key, foundational RISC-V open source projects
GCC, LLVM, Linux kernel, GLIBC, Python
> 150 toolchain bugs found via our fuzzer instances
Jeff Law/Ventana (and upstream GCC maintainer)
“We don’t commit anything into gcc for RISC-V that hasn’t passed the RISE gcc CI. Incredibly helpful!”
Build Farm: 2024Q4 Review
Eight existing projects running
RISE GCC pre-commit CI (Patrick O'Neill, Edwin Lu)
RISE GCC post-commit CI (Patrick O'Neill, Edwin Lu)
RISE GCC fuzzer CI (Patrick O'Neill, Edwin Lu)
RISE GCC microcontroller CI (Patrick O'Neill, Edwin Lu)
RISE GLIBC pre-commit CI (Patrick O'Neill, Edwin Lu)
RISE LLVM fuzzer CI (Patrick O'Neill, Edwin Lu)
RISE Linux Kernel CI (Björn Töpel)
RISE Python Wheels (Mark Ryan)
Two existing projects temporarily expanded
RISE GCC fuzzer CI (Patrick O'Neill, Edwin Lu)
RISE LLVM fuzzer CI (Patrick O'Neill, Edwin Lu)
Remaining GCP credits leveraged to greatly expand the number of fuzzer instances running (and thus the number of bugs we could find)
Thanks to Patrick, Edwin, and Björn for putting in extra work to make this possible!
One existing project shut down
RISE QEMU Aarch64 test system (Paul Walmsley, Max Chou)
No longer needed by RP005
Considerable volunteer time spent preparing for the Hetzner transition and monitoring LF/Hetzner progress
Google Cloud account closed out with ~$10,000 USD of credits unused (preserved as a safety margin)
All credits expired December 31, 2024
Thanks again to Google for the donation
Hetzner account was not set up in time to complete the server transition before the end of the year
RISE incurred some direct budget costs in 2025Q1
Discussed in following slides
Ran on GCP throughout January as we waited for the Hetzner account to be set up
Toolchain fuzzer instances temporarily shut down to reduce costs (non-critical services)
Required direct payment from RISE budget, as GCP credits expired EOY 2024
Migrated to new Hetzner infrastructure at the end of January
Fast execution saved RISE money
Credits
Björn Töpel (Rivos), Patrick O’Neill (Rivos), Edwin Lu (Rivos), Mark Ryan (Rivos)
Brian “Redbeard” Harrington (Red Hat)
Some challenges with the Google Cloud->Hetzner transition
Hetzner account not available for our use until end of January
Two month latency from when we requested it
Unplanned 30 hour outage at the end of February
Caused by a billing dispute
Adding external monitoring to catch outages sooner
Hetzner account migration at the beginning of March
Original Hetzner account not set up to bill in Euros
New account had to be created and instances migrated
No ability for RISE to directly track expenditures on Hetzner
Our accounts do not have these permissions
Going forward, these deep dives will not include budget reports
Two existing projects temporarily paused in January
RISE GCC fuzzer CI (Patrick O'Neill, Edwin Lu)
RISE LLVM fuzzer CI (Patrick O'Neill, Edwin Lu)
One existing project expanded (as planned)
RISE Linux Kernel CI (Björn Töpel)
Doubled the number of servers to provide additional test coverage
RISE Board Farm
Objective
Provide a range of Linux-capable RISC-V boards to run functionality and performance tests on CI-generated code
Investigate feasibility of providing developer access to boards
Status
No significant progress in 2024Q4 or 2025Q1
Build Farm relocation and emergency response taking up all available management bandwidth
Planning to ramp up in 2025Q2
Volunteers solicited!
RISE Developer Tools
Objective
Provide a full Linux system image build, boot, and development environment for use on both simulators (QEMU) and RISC-V hardware
Ideally combines cross and native development environment and native system software and userspace
Status
Nathan’s Gentoo build available for general use with cutting-edge software included
Luca Barbedo putting in a lot of effort here
How to productize/test?
Credits
Barna Ibrahim (Rivos): Co-chair
Björn Töpel (Rivos): Kernel CI Build Farm Project Admin, Build Farm Lead
Brian ‘redbeard’ Harrington (Redhat): Build Farm Administrator
Edwin Lu (Rivos): Toolchain Build Farm Project Admin
Mark Ryan (Rivos): Python Build Farm Project Admin
Nathan Egge (Google): TSC contact, Developer Tools Lead
Patrick O’Neill (Rivos): Toolchain Build Farm Project Admin
Paul Walmsley (SiFive): Co-chair
Mar 6, 2025
Deep Dive Language Runtimes - Ludovic HENRY
Status Update: Java
Support for Vector extension: continual work
Support for FP16, more compiler optimizations
Matching RVA23:
Added: Zicond, Zfa, Zvkt, Zvbb
Only missing: Zimop, Zcmop, Zcb, and Zawrs
Status Update: Go
Matching RVA23:
It’s a work-in-progress
Adding C, V, B, Zicond, Zfa, Zihintpause, Zihintntl, Zcb, Zvbb, Zawrs
RP001
Wiki is up-to-date to track work to be done
Status Update: Python
RP011: Python Package Support for RISC-V
Signed, work is ongoing
Official documentation: https://riseproject.gitlab.io/python/wheel_builder/
Status Update: Python
Upstream projects can distribute on RISC-V:
No clear date for AlmaLinux availability on RISC-V
RockyLinux should be available in May 2025 on RISC-V
Viable alternative to AlmaLinux
Work Prioritization
Wiki is up-to-date
Java: https://wiki.riseproject.dev/display/HOME/LR_00%3A+Java
Python: https://wiki.riseproject.dev/display/HOME/LR_01%3A+Python
Javascript: https://wiki.riseproject.dev/display/HOME/LR_06%3A+Javascript
Rust: https://wiki.riseproject.dev/display/HOME/LR_07%3A+Rust
WASM: https://wiki.riseproject.dev/display/HOME/LR_08%3A+WebAssembly
Please comment on mailing list for prioritization
Anything not listed you’d like to see?
Anything not as high on the priority list as you expected?
Deep Dive Compilers/Toolchains – Jeff Law
Apologies for last week, customer meeting I couldn’t miss
RP007
Hoping to see upstream engagement on what they’re finding/fixing
RP008
making great progress on finding real issues and either fixing them or getting them recorded for future work
Not sure if anyone has put their name in the hopper for leading the group. I expect my bandwidth to be limited going forward, though could probably help cover GCC if absolutely necessary
GCC– GCC 15 release cycle in progress, ETA May 1
Still fixing bugs, but nothing RISC-V specific that is particularly worrisome
Many optimizations across scalar and vector domains
CRC work was finally integrated
Cactu optimization work
Vector, emphasis on x264 perf and zvl128..zvl512
Function multi-versioning
Stack-clash mitigation
Items for 2025
Xz vectorization. POC shows ~12% on spec.
Another round of Zbs & extension removal improvements,
Fusion work (significant fixes, new cases, discovery)
Uarch support for vector costing/tuning
LLVM – LLVM 20 release imminent
No major RISC-V specific concerns for release according to Philip & Craig
Stack clash mitigations have been integrated
Function Multi-versioning
Vectorize xz search loop
Items for 1H2025
Folding “addi” into loads/stores more aggressively (done)
Shrink wrapping development done, just working through review comments
Landing pads for CFI (in flight)
Improvements for x264 vectorization, more work to be done
Feb 20, 2025
Deep Dive Simulator Emulator- Daniel Barboza
SE_02_004 (RP005) - QEMU RVV performance enhancements
Development completed, reviews ongoing in the ML. Performance enhancement up to 500% depending on vector configuration and workload
SE_01_021 - QEMU RVA23 profile support
Queued in the maintainer’s tree
Prerequisite of other items such as “RISC-V Server SoC Reference Board”
E-trace items (SE_01_024, SE_01_025, SE_01_026, SE_01_027)
New in 2025. Implementation of RISC-V Efficient Trace spec. Owner: Daniel Barboza (Ventana Micro)
Development ongoing
Other items under review in the QEMU mailing list:
SE_01_003 - QEMU WorldGuard support
SE_01_004 - QEMU IOPMP support
SE_01_022 - RISC-V Server SoC Reference Board
SE_01_005 - QEMU PCIe passthru on x86 hosts
SE_01_023 - QEMU RISC-V IOMMU Enhancements
Not yet sent for review
SE_01_022 - QEMU P Extension support
Items completed
SE_01_017 - QEMU ACPI SPCR Support for RISC-Vc
Feb 6, 2025
Kernel and Virtualization Deepdive- Anup Patel
What’s merged for Linux-6.14 ?
Linux-6.14-rc1 was released on 2nd February 2025
Noteworthy stuff merged for Linux-6.14:
Linux RISC-V
T-Head vector extensions support
KVM RISC-V
Svvptc, Zabha, and Ziccrse extension support for Guest/VM
Virtualize SBI system suspend extension for Guest/VM
Trap related exit statistics as SBI PMU firmware counters for Guest/VM
RVA23 profile: Discovery updates
HWPROBE additions in Linux-6.14
No updates
KVM ONE_REG additions in Linux-6.14
Zabha, Svvptc, and Ziccrse
Kernel HWPROBE (27-01-2024, wiki)
TBD - 7 (7.45%), NA - 47 (50%), COMPLETED - 40 (42.55%), TOTAL - 94
KVM ONE_REG (27-01-2024, wiki)
TBD - 24 (25.53%), NA - 13 (13.83%), COMPLETED - 57 (60.64%), TOTAL - 94
2024-1H: Project updates
2024-1H: Recently upstreamed projects
LK_03_023 - QEMU-KVM Zawrs support
LK_02_025 - KVM System Suspend Virtualization
LK_03_008 - QEMU-KVM AIA user-space irqchip_split support
2024-1H: Development status (27-01-2025, wiki)
TBD - 2 (4.08%), ONGOING - 1 (2.04%), COMPLETED - 46 (93.88%), TOTAL - 49
2024-1H: Upstreaming status (27-01-2025, wiki)
TBD - 3 (6.12%), ONGOING - 5 (10.21%), COMPLETED - 41 (83.67%), TOTAL - 49
2024-2H: Project updates
2024-2H: Recently development complete projects
LK_01_024 - Supervisor Counter delegation (Smcdeleg and Ssccfg) based perf
LK_01_025 - Control Transfer Record (Smctr and Ssctr) support in perf driver
LK_01_044 - Firmware Feature support
LK_01_045 - Message Proxy support
LK_01_046 - RPMI Clock driver using SBI MPXY
LK_02_028 - KVM Firmware Feature virtualization
LK_03_026 - KVMTOOL Svadu support
LK_03_034 - KVMTOOL Smnpm and Ssnpm support
2024-2H: Recently upstreamed projects
LK_02_027 - KVM Svvptc virtualization
2024-2H: Development status (27-01-2025, wiki)
TBD - 13 (35.14%), ONGOING - 1 (2.70%), COMPLETED - 23 (62.16%), TOTAL - 37
2024-2H: Upstreaming status (27-01-2025, wiki)
TBD - 18 (48.64%), ONGOING - 13 (35.14%), COMPLETED - 6 (16.22%), TOTAL - 37
Jan 30, 2025
Distro and Integration- Brian Harrington
The most recent discussion revolved around the development of a unified database for RISC-V processors and related tools, aiming to streamline information access and collaboration within the community. Additionally we discussed some needs/desired with regards to automated builders (specifically hosted by GitHub/GitLab). Here's a structured summary of the key points:
RISC-V Unified Database:
Hosted on GitHub at https://github.com/riscv-software-src/riscv-unified-db
Purpose: To compile comprehensive details about RISC-V processors, platforms, and associated tools, facilitating easier access for developers.
Related Items:
Reminder of https://riscv.builders , building / compiling software for RISC-V, though called out that it’s still insufficient for the u-boot development desired by members.
Nathan Egge provided a PDF about LLVM-Mingw, detailing its use for cross-compiling RISC-V applications on Windows, which is crucial for developers in Windows environments.
Jan 23, 2025
System Libraries Deep Dive- Nathan Egge
Multimedia (and other) RVI extensions
Feedback from VideoLAN community fed into RVI proposals
dot prod, vector abs-diff (SAD), zip/unzip
Continued collaboration after VDD 2024
Got feedback on signed variants of SAD extension proposal
Plan to set up meeting across RISE, RVI Vector SIG and VideoLAN / FFmpeg
Goal: early feedback on algorithms instructions would be used in
May guide instruction coding (params) and find edge cases *before* ratification
RISE presence at FOSDEM 2025
Attend RISC-V devroom (thanks Bjorn)
Concurrent open-media devroom for in person collaboration
Community still asking for more diverse hardware
Larger VLEN, OOO cores, different IP to cross validate algorithms
Software Optimization Progress
XNNPACK still a priority
Ken Unger (Microchip) patches in flight quantized kernel optimizations for RVV
PyTorch progress
Philip Reams (Rivos) open to collaborating and providing public RISC-V packages
Build system issues discussed
sleef build issues
Currently broken for cross-compilation, not an easy fix
New project hosted on RISE gitlab for Mbed-TLS
Developer Images
Luca Barbato (Gentoo) sent a ROMA II laptop for testing
Working to get this booting to check status of graphics stack
clang-20 released, contains some fixes for auto-vectorization
Need to check if this allows zvl256b
gcc progress made fixing issues raised by Luca, but not ready yet
Minor issues with rustc ebuild on RISC-V addressed by Luca
System Libraries Priorities - H1 2025
High profile, in-demand projects, e.g., Tensorflow, Chromium, etc.
Planning to finalize this in next System Libraries meeting Dec 10, 2024
Instructio timings for optimization guide
Potential to use llvm-exegesis to extract these for help with RVV optimizations
Capture missing vector instructions from multimedia projects [1]
Key Idea: Collect gaps in extension opcodes preventing efficient multimedia DSP functions, e.g., no transpose op, no dotprods, missing sign-unsign mults, etc.
Work with multimedia developers
Testing framework for upstream projects
Issues raised by vendors and OSS contributors about inconsistent benchmarking
Example project + source code with best practices for statistically significant data
More guest speakers!
2025
Dec 5, 2024
System Libraries Deep Dive
System Libraries Priorities - H1 2024
SL_00_001 bionic (Done)
SL_00_006 chromium-zlib (Done)
SL_01_002 dav1d (In progress)
Landed 16bpc blend functions, presented how to contribute RVV to dav1d at VDD https://people.videolan.org/~negge/vdd24.pdf
Andes patch pending https://code.videolan.org/videolan/dav1d/-/merge_requests/1735
SL_01_003 x264 (In progress)
Bytedance added RISC-V support to build system, patches in review
https://code.videolan.org/videolan/x264/-/merge_requests/155
SL_01_004 Pixman (In progress)
Samsung added optimized pixel format conversion and blending
SL_00_006 DPDK (In progress)
14x speed up on CRC operations from Bytedance
Developer Images
Latest image based on Bianbu 2.0 and can be found here [1]
Boots Banana Pi BPI-F3 and possibly other k1/m1 based boards
Clang-19.1.2
Past experiments results
clang-20 snapshots fail to build [2]
gcc-15 still has problems, but it is reported that gcc-trunk has the alignment problems fixed.
The rust build system seems to fail to pick the Gentoo cross compiler put in config.toml (I'll investigate further why)
Presented these images at the RISC-V 101 session and RVI devboard sig [3]
[1] https://dev.gentoo.org/~lu_zero/riscv/gentoo-linux-k1_dev-sdcard-2.0.img.xz
[2] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115789
[3] https://people.videolan.org/~negge/riscv101.pdf
Proposed RVV instructions for Multimedia
Initially discussed at RISC-V Summit EU 2024
Key Idea: Many implementers noticed the same ISA gaps porting multimedia libraries
Bytedance created a wiki page to track these instructions:
https://lf-rise.atlassian.net/wiki/spaces/HOME/pages/8588516/RISCV64+new+vector+instructions+requirements+for+video+multimediaVector transpose
Absolute difference
Zero-extended vmv.x.s
Rounded Shift Right Narrow,
Signed saturate and Narrow to Unsigned
Did a call for RISC-V Multimedia Instruction Wishlist at VDD 2024:
https://docs.google.com/presentation/d/16r4pT3YfI1UL5nX3na5SAnZ1DtHglbVPy64oPexwoN8/Collected 3 pages of notes, many overlap above
Signed to unsigned, e.g. vnclipsu
Changing SEW while preserving the ratio of LMUL
Changing rounding mode is slow on Kendryte K230 and SpacemiT K1
Missing integer absolute difference instruction, e.g., vabs (equiv. of vfabs)
Limited usage of register based vsetvl is OK
Optimization guide cautions against using vsetvl
Long discussion with hardware engineers at LLVM Dev Meeting Santa Clara
Under some circumstances it is OK to use vsetvl, e.g., as in dav1d
May be possible to use this in auto-vectorization loop unrolling to “fold” the tail so it shares the same code as main body, potentially reducing cost of enabling RVV
Register Pressure Example - 16bpc blend
Recall…
vwmulu.vv v24, v8, v16
vwmulu.vv v8, v12, v20
Section 5.2 Vector Operands
System Libraries Priorities - H1 2025
High profile, in-demand projects, e.g., Tensorflow, Chromium, etc.
Planning to finalize this in next System Libraries meeting Dec 10, 2024
Instruction timings for optimization guide