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- Improvement of if-conversion pass in GCC to handle SUBREG and zero/sign extended objects.
Use of ADD rather than IOR when possible- If-convert the conditional in the move_one_fast loop of deepsjeng
- Two approaches
- Improve min/max discovery in gimple which should simplify the conditional code to optimizable form in the RTL if-converter code
- Improve the RTL if-converter code to better handle multiple if-convertable instrutions
- Add backend pattern to recognize an if-then-else as a min/max
- Two approaches
- Cost model adjustments
- As touched on in upstream bug 112462, when we have a condition other than (reg) eq/ne (const_int 0) we need to bump the cost of using zicond as the condition will need canonicalization.
- Similarly we may need to bump the cost depending on the true/false arms
- May want to do some refactoring so that we can share code across costing & expansion.
Analysis has shown that the most common missed if-conversion cases for RISC-V are related to mode changing operators such as SUBREG, ZERO_EXTEND and SIGN_EXTEND which are commonly used when operating on 32bit objects for rv64.. ESWIN and Ventana have differing implementations in this space that need to be resolved. The core concern with the ESWIN implementation is that it directly modifies the objects in the IL, which in turn means that it's difficult (potentially impossible) to correctly handle certain cases (shifts). In contrast the Ventana implementation emits new IL for the converted sequence and deletes the old parts of the IL.
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