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- Jivan has a small patch which detects generation of some redundant sign/zero extensions in the RISC-V backend. This is not expected to produce any significant benchmark improvements, but mostly serves as a final catch for corner cases so that we don't have to debug them again. To date cases detected have all been due to expansion of builtins which perform overflow checking of basic integer operations.
- Eliminate the redundant sign extension after an inlined strcmp.
- Eliminate the redundant sign extension after an inlined memcmp
- Use Jivan's trick to expose the sign extended nature of SI/HI/QI mode return values.
- Investigate Ajit's work (IBM) to exploit cases where masking can be viewed as zero-extension within REE
- In REE handle cases like (any_extend:DI (ashift:SI )) where the extension can be replaced by a SUBREG and then push the SUBREG into the operands generating word sized operations. This helps code like this:
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Updates
- Add memcmp optimization to list
- strcmp optimization submitted upstream
- Breaking out additional items as 2H2024 work