About

These are two tasks carried forward from 1H2024 and some additional work identified in 2024

1. Jivan has a small patch which detects generation of some redundant sign/zero extensions in the RISC-V backend.    This is not expected to produce any significant benchmark improvements, but mostly serves as a final catch for corner cases so that we don't have to debug them again.  To date cases detected have all been due to expansion of builtins which perform overflow checking of basic integer operations.

   1. To date this has only triggered as a result of the expansion of arithmetic with overflow checking

   2. Probably still worth integrating

2. Eliminate the redundant sign extension after an inlined strcmp.

3. Eliminate the redundant sign extension after an inlined memcmp

4. sCC code generation will often need mixed modes and would benefit from Jivan's trick

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Dependencies

Status

Updates

Nov 7, 2024 

• Incomplete/New items moved to 2025.

Oct 12, 2024 

• Jivan's patch to avoid zero/sign extending a value already known to be appropriately extended has been integrated.

Sep 4, 2024

• Note that sCC expansion code can benefit from Jivan's trick as well and a patch implementing that has been integrated. 

Jul 25, 2024 

• Elimination of the redundant extension after inlined strcmp and memcmp are upstreamed.

• Add note on comparisons

Jul 10, 2024 

• Add memcmp optimization to list

• strcmp optimization submitted upstream

Jun 29, 2024

• Breaking out additional items as 2H2024 work