About
The ZiCondops extension provides a conditional zero primitive upon which subsets of conditional move and conditional arithmetic/logical operations can be implemented. Transforming control flow into conditional operations can improve code performance by eliminating branch mispredict costs as well as reducing the load on the branch predictors. The earlier in the optimizer pipeline these transformations are performed the more likely they are to expose secondary optimization opportunities as well since the transformations result in larger basic blocks (a fundamental unit of code most compiler optimizations work on).
This work consists of 4 subprojects:
Basic ZICondops patterns in the RISC-V target descriptionVRULL + Ventana + ESWIN
Improvements to generate those patterns early in the RTL optimizer pipelineVentana (primarily Raphael's work with bugfixing from Jeff) + ESWIN
Fixes to cost model to enable more conditional move generatinon- Improvements to the if-converter to consistently utilize the conditional zero primitive provided by ZICondops
- Mixed work from VRULL, Ventana & ESWIN
Evaluation of the initial implementation has indicated that idioms to implement 32 bit operations on rv64 are consistently not if-converted. Improvements to capture those cases are in progressitem is meant to track pieces of the 2H2023 effort that did not get fully integrated upstream in time for gcc-14.
- Improvement of if-conversion pass in GCC to handle SUBREG and zero/sign extended objects.
- Use of ADD rather than IOR when possible
Analysis has shown that the most common missed if-conversion cases for RISC-V are related to mode changing operators such as SUBREG, ZERO_EXTEND and SIGN_EXTEND which are commonly used when operating on 32bit objects for rv64.. ESWIN and Ventana have differing implementations in this space that need to be resolved. The core concern with the ESWIN implementation is that it directly modifies the objects in the IL, which in turn means that it's difficult (potentially impossible) to correctly handle certain cases (shifts). In contrast the Ventana implementation emits new IL for the converted sequence and deletes the old parts of the IL.
WRT ADD vs IOR. When there are no bits in common between the two input operands, ADD and IOR are equivalent from a functional standpoint. ADD should be slightly preferred over IOR because ADD has a higher likelihood of being implemented as a compressed instruction when compared to IOR (IOR only allows a subset of the register file to be used in compressed forms).
Stakeholders/Partners
RISE
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Ventana: 1 FTE, ~12 wks. Raphael Zinsly. Revamped basic support in preparation for upstreaming, support for conditional 32bit ops, conditional move support early in the compiler optimization pipelineVentana: Jeff Law. Integration of Raphael's work with upcoming changes from Philipp.Rivos: Oversight & review.
SiFive: Oversight
External:
VRULL: Philipp Tomsich. Initial work under contract to Rivos and Ventana. Ongoing updates
ESWIN: Submission of basic Zicond support, conditional move and limited improvements to ifcvtESWIN: Fei Gao
Dependencies
Status
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Updates
- eswin has posted updates to the generic if-converter, both those and the version used by Ventana are breaking x86, this needs to be understood and fixed before this work can move forward
- Cost model fixes integrated, resulting in more aggressive if-conversion and use of zicond
- Additional testcases from ESWIN integrated
- Leaves just the target independent changes to sort through
- Testcases from patch #3 from eswin's kit are upstreamed
- Patch which should fix the costing model issues enabling tests from patch #4 to get installed is ready for testing
- No progress on patch #5 (target independent improvements to if-conversion)
- One codegen fix and once ICE fix upstreamed
- Addition of xventanacondops on top of zicond
- Found and fixed missed case affecting CRC loop in coremark
- Still untangling generic changes. 3 significant implementations in play
- Cost model fixes still pending – critically important as we can't add the full suite of tests until that's fixed, hoping to wrap it up this week
- Target dependent bits to wire up zicond to conditional move support done & integrated
- Improvements to generic code to synthesize conditional arithmetic/logicals under review
- ESWIN's code looks to be more aggressive in many respects (good)
- But also less aggressive in handling sub-word cases
- Not sure yet on approach to be taken
- General upstream agreement that costing model needs work.
- Dependencies on binutils/qemu dropped as they've been resolved.
- Several bugs found & fixed in additional optimization patterns provided by ESWIN
- Costing model issues are deeper than anticipated. May spin out distinct project for that
- Initial bits to wire up zicond to implement conditional moves ready to land
- Basic Zicond support from ESWIN is the same as Ventana's internal bits and in-line with where VRULL was asked to go
- Basic support integrated
- Working on costing model which we ought to have sorted out 7/26.
- Next will be unifying the ESWIN and Ventana bits to enable limited conditional move support using Zicond
- After that we need to evaluate what if-converter bits are needed.
- Slow movement here has resulted in a "competing" implementation.
- Manolis from VRULL has started posting some of the generic work to facilitate use of Zicond/Xventanacondops
- Jeff from Ventana continues to fix bugs in code which exposes Zicond/Xventanacondops to tree→RTL expansion code (internal to Ventana right now, but definitely planned to upstream)
- Binutils dependency has been resolved (Zicondops will appear in binutils-2.41 in July)
- VRULL will repost their work. Ventana will coordinate with VRULL on review/updates
- Note QEMU dependency
- Consistent reporting of stakeholders/partners
- ZICondops binutils patch (re)approved
– Dates on or before June 15 are approximate
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- Remaining items from 2H2023 pulled into H12024 project.