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• Improvement of if-conversion pass in GCC to handle SUBREG and zero/sign extended objects.
• Use of ADD rather than IOR when possible
• If-convert the conditional in the move_one_fast loop of deepsjeng
  • Two approaches
    • Improve min/max discovery in gimple which should simplify the conditional code to optimizable form in the RTL if-converter code
    • Improve the RTL if-converter code to better handle multiple if-convertable instrutions
    • Add backend pattern to recognize an if-then-else as a min/max

Analysis has shown that the most common missed if-conversion cases for RISC-V are related to mode changing operators such as SUBREG, ZERO_EXTEND and SIGN_EXTEND which are commonly used when operating on 32bit objects for rv64..  ESWIN and Ventana have differing implementations in this space that need to be resolved.  The core concern with the ESWIN implementation is that it directly modifies the objects in the IL, which in turn means that it's difficult (potentially impossible) to correctly handle certain cases (shifts).  In contrast the Ventana implementation emits new IL for the converted sequence and deletes the old parts of the IL.

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Ventana: Raphael Zinsly, Jeff Law, Robin Dapp

External:

ESWIN: Fei Gao

Dependencies

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Updates

05 Jun 2024 

• Robin has submitted a potential fix for detection of min/max in deepsjeng, which in turn should allow fixing the missed if-conversion in deepdjeng
• Jeff has provided ESWIN with Ventana/code to handle sub-word objects.

25 Apr 2024 

• ESWIN has upstreamed their change to use ADD rather than IOR for generalized conditional moves.  While technically not allowed at this stage of the gcc-14 cycle, it was approved as an exception given how safe it should be.
• Ventana is de-emphasizing extension and subword cases.  We'd be happy to provide the work-in-progress to ESWIN or anyone else that wants to try and further improve if-conversion to handle those cases.

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