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This item is meant to track pieces of the 2H2023 effort that did not get fully integrated upstream in time for gcc-14.


  • Improvement of if-conversion pass in GCC to handle SUBREG and zero/sign extended objects.
  • Use of ADD rather than IOR when possible
  • If-convert the conditional in the move_one_fast loop of deepsjeng
    • Two approaches
      • Improve min/max discovery in gimple which should simplify the conditional code to optimizable form in the RTL if-converter code
      • Improve the RTL if-converter code to better handle multiple if-convertable instrutions
      • Add backend pattern to recognize an if-then-else as a min/max
  • Cost model adjustments
  • As touched on in upstream bug 112462, when we have a condition other than (reg) eq/ne (const_int 0) we need to bump the cost of using zicond as the condition will need canonicalization.
  • Similarly we may need to bump the cost depending on the true/false arms
  • May want to do some refactoring so that we can share code across costing & expansion.

Analysis has shown that the most common missed if-conversion cases for RISC-V are related to mode changing operators such as SUBREG, ZERO_EXTEND and SIGN_EXTEND which are commonly used when operating on 32bit objects for rv64..  ESWIN and Ventana have differing implementations in this space that need to be resolved.  The core concern with the ESWIN implementation is that it directly modifies the objects in the IL, which in turn means that it's difficult (potentially impossible) to correctly handle certain cases (shifts).  In contrast the Ventana implementation emits new IL for the converted sequence and deletes the old parts of the IL.


WRT ADD vs IOR.  When there are no bits in common between the two input operands, ADD and IOR are equivalent from a functional standpoint.  ADD should be slightly preferred over IOR because ADD has a higher likelihood of being implemented as a compressed instruction when compared to IOR (IOR only allows a subset of the register file to be used in compressed forms).

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Page Properties


Development

Status
colourBlueGreen
titleIN PROGRESSCOMPLETE


Development Timeline1H2024
Upstreaming

Status
colourBlueGreen
titleIN PROGRESSCOMPLETE



Upstream Version

gcc-15 (target)

(Spring 2025)





Contacts

Raphael Zinsly (Ventana)

Jeff Law (Ventana)


DependenciesNone



Updates

 

  • Items which were not completed in 1H2024 moved to new work item for 2H2024.

 

  • Robin has submitted a potential fix for detection of min/max in deepsjeng, which in turn should allow fixing the missed if-conversion in deepdjeng
  • Jeff has provided ESWIN with Ventana/code to handle sub-word objects.

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