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This item is meant to track pieces of the 2H2023 effort that did not get fully integrated upstream in time for gcc-14.
- Improvement of if-conversion pass in GCC to handle SUBREG and zero/sign extended objects.
Use of ADD rather than IOR when possible- If-convert the conditional in the move_one_fast loop of deepsjeng
- Two approaches
- Improve min/max discovery in gimple which should simplify the conditional code to optimizable form in the RTL if-converter code
- Improve the RTL if-converter code to better handle multiple if-convertable instrutions
- Two approaches
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WRT ADD vs IOR. When there are no bits in common between the two input operands, ADD and IOR are equivalent from a functional standpoint. ADD should be slightly preferred over IOR because ADD has a higher likelihood of being implemented as a compressed instruction when compared to IOR (IOR only allows a subset of the register file to be used in compressed forms).
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Ventana: Raphael Zinsly, Jeff Law
External:
, Robin Dapp ESWIN: Fei Gao
External:
Dependencies
Status
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Updates
- Items which were not completed in 1H2024 moved to new work item for 2H2024.
- Robin has submitted a potential fix for detection of min/max in deepsjeng, which in turn should allow fixing the missed if-conversion in deepdjeng
- Jeff has provided ESWIN with Ventana/code to handle sub-word objects.
- ESWIN has upstreamed their change to use ADD rather than IOR for generalized conditional moves. While technically not allowed at this stage of the gcc-14 cycle, it was approved as an exception given how safe it should be.
- Ventana is de-emphasizing extension and subword cases. We'd be happy to provide the work-in-progress to ESWIN or anyone else that wants to try and further improve if-conversion to handle those cases.
- Ventana has an internal adjustment to the generalized conditional move code to use ADD rather than IOR. It will be submitted upstream as soon as gcc-15 is open for development.
- Ventana also has proof of concept code for the deepsjeng issue
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