From the meeting on Feb, 18th 2025, here are some of the software stacks that we are interested in contributing to.
Software Project | Description | Interests |
|---|---|---|
SLEEF https://github.com/shibatch/sleef
| Used by PyTorch and other projects for complex math operations (quad, dft, fft) on CPU. It supports RISC-V fully since 3.6.1 | Rivos - Ludovic Henry |
OpenBLAS https://github.com/OpenMathLib/OpenBLAS/
| Industry standard for BLAS operations. Used by every AI/ML framework out there. It supports RISC-V RVV 128/256/512 bits already. The implementation is currently optimized for large square matrices which aren’t the typical shapes in AI/ML workloads. There is already support to pick different kernels based on the matrix shape for x86, we need to leverage that mechanism on RISC-V as well | Microchip - Ken Unger |
Eigen https://gitlab.com/libeigen/eigen/
| Eigen is a C++ template library for linear algebra: matrices, vectors, numerical solvers, and related algorithms. Used by PyTorch, Tensorflow, and Tensorflow-Lite (LiteRT). It doesn’t support RISC-V at all at the moment. There is an open issue and a corresponding open MR but there hasn’t been much activity over the past 5 months | Microchip - Ken Unger |
oneDNN https://github.com/oneapi-src/oneDNN | It provides a DNN API (similar to cuDNN) and it’s used in lots of places. It is already functional on RISC-V (per the documentation), but it is still experimental and it’s unclear how optimized it is with RVV. | Rivos - Ludovic Henry |
XNNPACK https://github.com/google/XNNPACK/
| There has been contributions from SiFive and Microchip, but contributions are slow to get merged. Contributions are being tracked in https://docs.google.com/spreadsheets/d/1PZAzBSqpdwoNgkxgrnmf5DDsZBzC_GEh/view We need to identify which intrinsics are critical to the models we care for. Notes:
| Microchip - Ken Unger |
PyTorch CPU https://github.com/pytorch/pytorch
| This work focused on PyTorch operators themselves, and not the dependencies used by PyTorch like OpenAI Triton, SLEEF, etc. A blocker is (was?) the availability of hardware to test on. Patches from SiFive were rejected for this reason There is an open PR to integrate cross-compilation support to CI. There would still be work to optimize many of the PyTorch Operators using RVV | Alibaba - @Binhua Wang |
IREE https://github.com/iree-org/iree | Interest is in the context of using it as a PyTorch compiler backend (see https://pytorch.org/docs/stable/torch.compiler.html for details) | Andes - @Ruinland Tsai |
OpenAI Triton https://github.com/triton-lang/triton | BOSC - @David Gao | |
Scikit-Learn https://github.com/scikit-learn/scikit-learn/ | scikit-learn already works out-of-the-box on RISC-V. However to reach better performance, Intel provides scikit-learn-intelex on x86 which is based on oneDAL. Rivos has already done the work to accelerate oneDAL on RISC-V, but we now need to provide a similar plugin to scikit-learn-intelex for RISC-V to bridge the worlds of scikit-learn and oneDAL. | Rivos - Ludovic Henry |
LiteRT (Tensorflow-Lite) https://github.com/google-ai-edge/litert | SiFive - @Hong-Rong Hsu | |