About
The vsetvli insertion pass currently runs late in the SSA portion of the pre-RA pipeline. This is before instruction sheduling and register allocation.
The vsetvli instruction act as instruction scheduling barriers. The physical register dependencies on VL and VTYPE introduced prevent register allocation from re-materializing instructions like vmv.v.i.
At the LLVM developer meeting in the fall 2023, we discussed a pipeline structure like this
- Leave SSA form
- Machine scheduling
- Register allocate vector registers
- vsetvli insertion
- Register allocate scalar registers
- This allows us to allocate the GPR updates needed for registers needed by vsetvli instructions.
Stakeholders/Partners
RISE:
SiFive: Piyou Chen (Lead Developer), Craig Topper
External:
Igalia: Luke Lau
Dependencies
Status
Updates
- Main patch landed May 20.
- Project added based on in progress work. https://github.com/llvm/llvm-project/pull/70549