Skip to end of metadata
Go to start of metadata

You are viewing an old version of this page. View the current version.

Compare with Current View Page History

« Previous Version 2 Next »

About

Performance will turn to be one of the key factors of competitiveness when it's going to the segments such as client/server/hpc. Currently, most software optimizations on RISC-V are performed on QEMU or non-representative hardware with limited resources, and there is no performance CI yet.


We need a performance CI on real hardware to improve the performance of key software on RISCV.

Project Scope

Create a performance CI for key software running on real hardware, provide the performance trends of software

  • show the progress of performance improvement (the bkm of one software may apply to others, so that the whole ecosystem benefits)
  • find the performance regressions

Components and Repos

  1. Performance CI software part, including monitor the code changes, run the benchmarks and dashboard to show the results
  2. Benchmarks for key software
  3. Labs with representative hardware

Stakeholders and Partners

  • RISE - Intel leads the effort to build the CI
  • RISE - Infra WG for reusable efforts
  • RISE - WGs provide the benchmarks of key software
  • Opensource Community of the key software

Measure of Success

  • M1 - CI setup
  • M2 - benchmarks integrated
  • M3 - opensource engagement with the performance trend chart

RISE Requirement

  • Lab for hardware hosting

Status

Development

ONGOING


Development Timeline1H 2024
Upstreaming

TBD


Upstream Version

N/A


Contacts

Fei Wu  (Intel)


Dependencies

  • No labels