DP_10_003 - Build performance CI infrastructure
About
Performance will turn to be one of the key factors of competitiveness when it's going to the segments such as client/server/hpc. Currently, most software optimizations on RISC-V are performed on QEMU or non-representative hardware with limited resources, and there is no performance CI yet.
We need a performance CI on real hardware to improve the performance of key software on RISCV.
Project Scope
Create a performance CI for key software running on real hardware, provide the performance trends of software
- show the progress of performance improvement (the bkm of one software may apply to others, so that the whole ecosystem benefits)
- find the performance regressions
Components and Repos
- Performance CI software part, including monitor the code changes, run the benchmarks and dashboard to show the results
- Benchmarks for key software
- Labs with representative hardware
Stakeholders and Partners
- RISE - Intel leads the effort to build the CI
- RISE - Infra WG for reusable efforts
- RISE - WGs provide the benchmarks of key software
- Opensource Community of the key software
Measure of Success
- M1 - CI infrastructure development done
- M2 - running on one or two software with benchmarks integrated
- M3 - opensource engagement with the performance trend chart
RISE Requirement
- Lab for hardware hosting
Status
Development | ONGOING | |
---|---|---|
Development Timeline | 1H 2024 | |
Upstreaming | TBD | |
Upstream Version | N/A | |
Contacts | Fei Wu (Intel) | |
Dependencies |