About
These are two tasks carried forward from 1H2024 and some additional work identified in 2024
- Jivan has a small patch which detects generation of some redundant sign/zero extensions in the RISC-V backend. This is not expected to produce any significant benchmark improvements, but mostly serves as a final catch for corner cases so that we don't have to debug them again. To date cases detected have all been due to expansion of builtins which perform overflow checking of basic integer operations.
- Eliminate the redundant sign extension after an inlined strcmp.
- Use Jivan's trick to expose the sign extended nature of SI/HI/QI mode return values.
- Investigate Ajit's work (IBM) to exploit cases where masking can be viewed as zero-extension within REE
- In REE handle cases like (any_extend:DI (ashift:SI )) where the extension can be replaced by a SUBREG and then push the SUBREG into the operands generating word sized operations. This helps code like this:
void foo(unsigned char *data, unsigned int lo_bit) {
unsigned int mask = ((1UL << 1) - 1) << lo_bit;
*data = (*data & ~mask) | ((1 << lo_bit) & mask);
}
One the unnecessary extension is eliminated a simple backend pattern can be used to simplify all that to a simple lb+bset+sb.
Stakeholders/Partners
RISE:
Ventana: 1 FTE Jivan Hakobyan and Jeff Law
Rivos: Vineet (part time)
External:
Dependencies
Status
Updates
- Breaking out additional items as 2H2024 work