About
Based on previous work and discussion:
https://github.com/intel/valgrind-rvv/tree/poc-rvv
In order to upstream RVV support in Valgrind, we need to introduce a generic scalable vector IR as a common framework, which can accommodate both ARM SVE and RISCV RVV.
Project Scope
The task - is the re-work of LLDB RegisterInfo and related classes to separate register info arrays for GPR/FPR/VPR and detect which one(s) should be used by enabling them in "opt_regsets" flags
A POC of scalable vector IR design in valgrind, which supports both typical ARM SVE and RVV instructions. Based on the patch, start community discussion for aligned direction.
Components and Repos
https://github.com/intel/valgrind-rvv/
Measure of Success
POC should support both ARM SVE and RVV sample apps, using a generic vector IR framework.
RISE Requirement
None