EDK2_00_02_01 Plan
No. | Doc / Feature / Task / Bug | Descritption | Deliverable | Prioriy (Low - Middle - High) | Estimation of Due Date | Owner | Stataus | Other Comments |
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#1 | Design document | Design document describe how StandaloneMM for Risc-V working such as how
| High Level Design Document | High | 07/15/23 | Tuan - Ventana | Done | EDK2_00_02_02 Standalone MM design (draft) |
#2 | Staging Repo | Create staging branch everyone can contribute to | Code Repo | High | 06/30/23 | Yong - Intel | Done | Baseline code has been pushed to the staging branch https://github.com/tianocore/edk2-staging/tree/RiscV64StandaloneMm |
#3 | Unify MM payload for ARM and RISC-V | The MM payload is based on ARM TF. To support for RISCV, the structure needs to be more standard to support both Arm and RiscV. I am seeing the mixing code for RISC-V that exists in “ARM’ source code such as: StandaloneMmCoreEntryPoint/Arm/CreateHobList.c, StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/SetPermissions.c | Code | High | 07/20/23 | Tuan - Ventana | Done | |
#4 | Unify MM entrypoint API for ARM and RISC-V | PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT needs to be renamed to common name for ARM and RISC-V. | Code | High | 07/20/23 | Tuan - Ventana | Done | |
#5 |
| SBI calling from Standalone MM should using payload data from standard SBI Ext of APTEE or Penglai | ||||||
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| Defer | Defer for SBI spec, do we need a dedicated SBI call for MM ? | |||||
#7 | Hob re-structure | Hob structure needs to be common. Sources.AARCH64, Sources.ARM, Sources.RISCV64] Arm/StandaloneMmCoreHobLib.c Arm/StandaloneMmCoreHobLibInternal.c | Code | High | 07/31/23 | Yong - Intel | Done | https://github.com/tianocore/edk2-staging/blob/RiscV64StandaloneMm/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/StandaloneMmCoreHobLib.inf |
#8 | MM entrypoint with HOB address | HOB can be added to A1 of StandaloneMM entry point | Code | High | 07/31/23 | Yong - Intel | Done |
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#9 | Qemu to support Secure UART | Qemu to support Secure UART | Code | High | Yong - Intel | In-Progress | Patch to be upstream https://lore.kernel.org/all/20230425073509.3618388-1-yong.li@intel.com/ | |
#10 | Qemu to support flash1 storage variable | Qemu to support flash1 storage variable | Code | High | 07/31/23 | Yong - Intel | Done | Rebased with the latest EDK2 repo. flash1 has been used for storage variable |
#11 | StandaloneMm as a Secure Payload of M-Mode FW | Need build the sign and authentication flow | PoC | Middle | TBD | |||
Invalid | In current implementation, the MM firmware is in (H)S mode for both OpenSBI or COVE implementation | |||||||
#13 | Evaluate StandaloneMmPkg sPMP based TEE FW (eg: Penglai TEE) | StandaloneMmPkg as TEE payload | PoC | Middle | TBD | In-Progress | EDK2_00_02_04 Evaluate with OpenSBI | |
#14 | Evaluate StandaloneMmPkg in TVM (eg: Salus/AP-TEE) | Currently the CoVE dose not fit the model that StandaloneMM requires access to the I/O directly through TVM. There could be potential AP-TEE / TEEIO spec change or definition. | PoC | Middle | Dhaval Samuel - Rivos Tuan - Ventana | In-Progress | EDK2_00_02_05 Evaluate with Salus Potential AP-TEE / TEEIO spec change or definition, definitly need help from Rivos for this task together | |
#15 | Evaluate StandaloneMmPkg in dedicated HW core(eg: T-Head TH1520) | TH1520 has a dedicate Cortex M3 Core for TEE, evaluate to isolate the flash storage to the TEE core and also run the StandaloneMmPkg on the TEE core and use Mbox to communicate between TEE core and RISC-V AP core. | PoC | Middle | TBD | May need involve T-Head | ||
#16 | Prototype StandaloneMmPkg and Secure Storage service in VisionFiveV2 | The flash storage service has been enabled in EDK2 by StarFive. Penglai is also porting their sPMP based TEE solution on VisionFIveV2, probably can combine all these things together with StandaloneMmPkg and prototype a demo | PoC | Middle | TBD | Depends on flash storage isolation on VisionFiveV2, an also the Penglai TEE enablement on VF2. Furthermore both Penglai and StarFive are not RISE member. | ||
#17 | Prototype StandaloneMmPkg with SiFive WorldGuard | PoC | Middle | TBD |