Debug and Profiling WG - Projects

Owned by Evan Harrison
Last updated: Nov 19, 2024 by Xiao W Wang
2 min read
Topic IDTopic NamePriorityDevelopmentUpstreamingDependencyTentative ETACompanyContactComments
Valgrind (00)
DP_00_001Valgrind vector supportHighInProgressInProgress
Q4 2023Intelfei2.wu@intel.com1. RV on Valgrind w/o Vector: https://github.com/petrpavlu/valgrind-riscv64
2. this task to support RVV framework + selected instructions on valgrind
DP_00_002Valgrind(mainly focus on the vector instruction support)MediumInProgressUnknown
?T-Headyunhai.syh@alibaba-inc.comhelper function based RVV implementation: https://github.com/rjiejie/valgrind-riscv64
DP_00_003ValgrindLowUnknownUnknown
Q3 2023Ventanajlaw@ventanamicro.com

Basic rv64 functionality to run Linux binaries correctly. Then support for the extensions in RVA22/RVA23.

DP_00_004Valgrind bitmanip, V, Zvk, etc. supportMediumUnknownUnknown
2024SiFive/Intel/CAS
Better to break down the task into B-ext/V-ext/Zvk subtasks, so we can co-ordinate the effort.
DP_00_005Valgrind scalable vector IRMediumUnknownUnknown
2024Intel

xiao.w.wang@intel.com

To introduce a unified scalable vector IR design to accommodate both ARM SVE and RISCV RVV
DP_00_006Support mulhsu insnMediumCompletedInProgress
2024Intelxiao.w.wang@intel.comhttps://github.com/petrpavlu/valgrind-riscv64/pull/22
DP_00_007Support all "csr*i" insnsMediumInProgressUnknown
2024Intelxiao.w.wang@intel.com
GDB (01)
DP_01_001GDBLowInProgressUnknown
 Q1 2024BOSCzhangjian@bosc.ac.cnHardware Watchpoints,Inferior function calls
DP_01_002Evaluate GDB status on RISC-VMediumUnknownUnknown

Andeshellosun@andestech.comhttps://lf-rise.atlassian.net/wiki/pages/viewpage.action?pageId=8585968
DP_01_003Add Zc support to GDB SimulatorMediumInProgressNotStarted
Q3 2023Imaginationsimon.harvey@imgtec.com

https://lf-rise.atlassian.net/wiki/display/HOME/DP_01_003+-+GDB+Simulator+-+Add+Zc+support

DP_01_004Add native Linux support for dump vector register contentMediumInProgressInProgress

SiFive

carsten.gosvig@sifive.com

info vector works for remote GDB but not when running natively

DP_01_005Add support for vector and scalar _Float16 typeMediumUnknownUnknown

SiFivecarsten.gosvig@sifive.com

https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/main/doc/rvv-intrinsic-spec.adoc#floating-point-types

DP_01_006Add support for vector and scalar __bf16 typeMediumUnknownUnknown

SiFivecarsten.gosvig@sifive.com

https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/main/auto-generated/bfloat16/intrinsic_funcs.adoc

DP_01_007Add support for landing padsHighUnknownUnknown

SiFivecarsten.gosvig@sifive.com

GDB must not set SW breakpoint on lpad instruction, but on the next instruction

DP_01_008Add support for shadow stackUnknownUnknownUnknown

SiFivecarsten.gosvig@sifive.com

GDB should support inspection&modification of the shadow stack

DP_01_009Add support for pointer maskingUnknownUnknownUnknown

SiFivecarsten.gosvig@sifive.com

GDB needs to unmask addresses that are still masked before using

LLDB (02)
DP_02_001LLDB for RV64LowUnknownUnknown

SiFivehttps://reviews.llvm.org/D62732https://reviews.llvm.org/D62732
DP_02_002Evaluate LLDB status on RISC-VMediumUnknownUnknown

Andeshellosun@andestech.comhttps://lf-rise.atlassian.net/wiki/pages/viewpage.action?pageId=8585968
DP_02_003Support coredumps for RV64MediumCompletedCompleted

Samsung

alexey.merzlyakov@samsung.com

https://github.com/llvm/llvm-project/pull/93297
DP_02_004FPR to be enabled/disabledLowCompletedCompleted

Samsungalexey.merzlyakov@samsung.com

For non-FP setups, like RV64IMAC, we need to have optionally disabled FPR on them

https://github.com/llvm/llvm-project/pull/104547

gprofng (03)
DP_03_001gprof-ngLowUnknownUnknown
Q4 2023Ventanajlaw@ventanamicro.com

Basic support for RV, particularly as it moves into the datacenter. Probably not that important on the embedded side.

Perf (04)
DP_04_001Userspace Cycle/Instret accessHighCompletedCompleted
Q3 2023Rivos

Alexandre Ghiti <alexghiti@rivosinc.com>


DP_04_002Perf event discovery/encoding from json fileMediumDoneNotStarted
Q1 2024Rivosatishp@rivosinc.com
DP_04_003Perf CTR (equivalent of x86 LBR) supportMediumDoneNotStarted
Q1 2024Rivos, SiFive

atishp@rivosinc.com, eric.lin@sifive.com


DP_04_004Perf CTR call stack mode supportMediumUnknownUnknown
Q1 2024Rivos, SiFive

atishp@rivosinc.com, eric.lin@sifive.com


Sanitizer (05)
DP_05_001Address sanitizerHighCompletedInProgress
2024T-Headyunhai.syh@alibaba-inc.comsupport RV32I in LLVM and GCC, research on optimization cooperate with Memory tagging extension
ToolChain (06)
DP_06_001riscv-gnu-toolchainUnknownUnknownUnknown

SiFivekito.cheng@sifive.com
DP_06_002binutilsUnknownUnknownUnknown

SiFivekito.cheng@sifive.com
DP_06_003ILP32 PSABIMediumInProgressUnknown
2024SiFivekito.cheng@sifive.com

PLCT guys has init implmenation, but need more survey for other ilp32 ABI like x32, ilp32/aarch64 and MIPS n32

DP_06_004DWARF representation for RVVUnknownUnknownUnknown

Red Hat

DynamoRIO (07)
DP_07_001DynamoRIO initial supportMediumInProgressCompleted
2024Rivosadlr@rivosinc.comWe kicked off the inital work and posted it upstream, but haven't been able to continue it
DP_07_002DynamoRIO basic supportMediumCompletedCompleted
H2 2023ISCASliuyang22@iscas.ac.cnCore module is now partially usable, part of the clients are also working. All of the work has been upstreamed.
https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/621mLGYsYz0?pli=1
DP_07_003DynamoRIO drcachesim & drcov supportHighInProgressInProgress
H2 2024ISCASliuyang22@iscas.ac.cn
DP_07_004DynamoRIO V extension supportHighInProgressInProgress
H2 2024ISCASliuyang22@iscas.ac.cn
DP_07_005DynamoRIO enable remaining tests that are also supported by AArch64MediumInProgressInProgress
H2 2024ISCASliuyang22@iscas.ac.cn
DP_07_006DynamoRIO RISC-V specific documentationMediumNotStartedNotStarted
H2 2024ISCASliuyang22@iscas.ac.cn
OpenLink (08)
DP_08_001openLink unifed debug probe protocol and firmwareMediumCompletedNotStarted
2024T-Headyunhai.syh@alibaba-inc.com
eBPF (09)
DP_09_001Evaluate status on RV: bpftraceMediumCompletedCompleted
2024T-Headcp0613@linux.alibaba.com

https://github.com/iovisor/bpftrace

The mainline already supports RV, we are already using it, please pay attention to enable kernel CONFIG.

DP_09_002Evaluate status on RV: bccMediumCompletedCompleted
2024T-Headcp0613@linux.alibaba.com

https://github.com/iovisor/bcc

The mainline already supports RV, we are already using it, please pay attention to enable kernel CONFIG.

DP_09_003Evaluate status on RV: ciliumUnknownUnknownUnknown




DP_09_004Evaluate status on RV: bpftuneUnknownUnknownUnknown




DP_09_005bpf JIT optimization based on Zba extensionMediumCompletedInProgress
2H 2024Intelxiao.w.wang@intel.compatches are partial merged
Performance Benchmarking and Analysis (10)
DP_10_001LKP framework enablement on RISC-VHighInProgressInProgress
2H2023Intelxiao.w.wang@intel.comhttps://github.com/intel/lkp-tests.git, build robot for riscv is already working
DP_10_002LKP workload enablement on RISCV-VMediumUnknownUnknown

Intelxiao.w.wang@intel.com
DP_10_003Build performance CI infrastructureMediumUnknownUnknown

Intelxiao.w.wang@intel.com
Simpleperf
DP_11_001Simpleperf (primarily used on Android)HighUnknownUnknown
1H2024SiFivekevin.mills@sifive.com
OpenOCD
DP_12_001Evaluate OpenOCD status on RISC-VUnknownUnknownUnknown

Andeshellosun@andestech.comhttps://lf-rise.atlassian.net/wiki/pages/viewpage.action?pageId=8585968