• About
• Project Scope and Timelines
• Components and Repos
• Stakeholders and Partners
• Dependencies
• Measure of Success
• RISE Requirements
• Status

About

The RISC-V IOMMU specification is now ratified as-per the RISC-V international process [1]. The latest frozen specifcation can be found at: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf

This project aims to introduce a RISC-V IOMMU device emulation implementation with two stage address translation logic, device and process translation context mapping and queue interfaces, along with riscv/virt machine bindings (patch 5) and memory attributes extensions for PASID support (patch 3,4).

This work is based on incremental patches created during RISC-V International IOMMU Task Group discussions and specification development process, with original series available in the the maintainer's repository branch [2].

References:

[1] - https://wiki.riscv.org/display/HOME/Specification+Status

[2] - https://github.com/tjeznach/qemu/tree/tjeznach/riscv-iommu-20230719

Project Scope and Timelines

The project will take place during the QEMU 8.2 development cycle.

Components and Repos

Upstream Qemu.

Current version of the patches:

https://lore.kernel.org/qemu-riscv/cover.1689819031.git.tjeznach@rivosinc.com/

Stakeholders and Partners

Other QEMU for RISC-V contributors, including:

• RISE
  • Tomasz Jeznach
  • Daniel Henrique Barboza
• External
  
  • Alistair Francis (QEMU for RISC-V maintainer)

Dependencies

No dependencies.

Measure of Success

An accepted and tested design and implementation by end of 2H23 (slated for merging).

RISE Requirements

None (not accounting any of existing engineering investment against RISE resources).

Status