RISE Compiler/Toolchain Projects Tracking
- Evan Harrison
- hiraditya
Owned by Evan Harrison
| Topic ID | Topic Name | Priority | Development | Upstreaming | Dependency | Tentative ETA | Company | Contact | Comments |
| GCC (00) | |||||||||
| CT_00_001 | Autovectorization (basic) | High | Completed | Completed | PSABI Vector specification | Q2 2024 | Rivos, Intel, Ventana | Jeff Law (Ventana) rufus@andestech.com jim@andestech.com Ken Unger? Andrew de los Reyes (Rivos) Pan Li (Intel) | Planning an unofficial branch off the gcc-13 release with backports of autovect work. Available to community at large (June 2023) |
| CT_00_002 | Inlined subword atomics, forward compatible mappings, optimizations for Ztso | High | Completed | Completed | Q3 2023 | Google, Rivos, Ventana | Jeff Law (Ventana) | To be included in gcc-13.2 release in Aug 2023, significant downstream dependencies | |
| CT_00_003 | Redundant Extension Elimination (GCC) | Medium | InProgress | InProgress | Ventana | Jeff Law (Ventana) | Expose sign-extending sematics of 32bit ops in rv64, reduces dynamic instruction counts by about .5% across specint2017. RAU's contribution | ||
| CT_00_004 | Address reassociation (GCC) | Medium | InProgress | InProgress | Ventana | Jeff Law (Ventana) | Reassocating after register elimination, VRULL's work | ||
| CT_00_005 | If-conversion (GCC ) | Medium | Completed | InProgress | Ventana | Jeff Law (Ventana) efriedma@quicinc.com | ZICond target support and middle end improvements | ||
| CT_00_006 | Zfa support (GCC) | Medium | Completed | Completed | Ventana Rivos | Jeff Law (Ventana) | |||
| CT_00_007 | Fusion support (GCC) | Medium | Completed | NotStarted | Ventana | Jeff Law (Ventana) | Keep fused ops together to improve performance | ||
| CT_00_008 | Backtracing (better in debugger group?) | Unknown | InProgress | InProgress | Intel, | Andrei Warkentin (Intel) efriedma@quicinc.com | DWARF/CFI is not appropriate for firmware environments | ||
| CT_00_009 | CRC Optimization (GCC) | Medium | InProgress | NotStarted | Ventana | Jeff Law (Ventana) | Helps coremark, but more importantly 200+ implementations in distros | ||
| CT_00_010 | Long branch support (GCC) | Medium | Completed | Completed | Ventana | Jeff Law (Ventana) | Support for functions > 1M in size | ||
| CT_00_011 | Stack clash (GCC) | Medium | Unknown | Unknown | Ventana | Jeff Law (Ventana) | Distro blocker (Fedora) | ||
| CT_00_013 | Autovectorization (improvements) | High | InProgress | InProgress | PSABI Vector specification | Q2 2024 | Rivos, Intel, Ventana | Jeff Law (Ventana) rufus@andestech.com jim@andestech.com Ken Unger? Andrew de los Reyes (Rivos) Pan Li (Intel) | Planning an unofficial branch off the gcc-13 release with backports of autovect work. Available to community at large (June 2023) |
| CT_00_012 | Inline expansion of mem* and str* | Medium | InProgress | InProgress | |||||
| CT_00_14 | Common syntax for target attribute (GCC) | Medium | Completed | InProgress | Allows for specification of target switches on a per-function basis. Prereq for function multiversioning | ||||
| LLVM (01) | |||||||||
| CT_01_001 | Autovectorization (basic) | High | InProgress | InProgress | PSABI Vector Specification | Q3 2023 | Rivos, Google, Imagination, MediaTek, Andestech, SiFive, Ventana | preames@rivosinc.com Alexey Bataev (SiFive) efriedma@quicinc.com | Partially lit up in LLVM 16, major development in flight for LLVM 17 which should release in Q3 2023 |
| CT_01_002 | Forward compatible atomics mappings | High | Completed | Completed | Q2 2023 | Google, Rivos, Ventana | Nathan Egge (Google) efriedma@quicinc.com | To be included in LLVM 17 release in Q3 2023, significant downtream dependencies | |
| CT_01_003 | Shadow Stack (LLVM) | High | InProgress | NotStarted | PSABI specs to allow x3 to become OS specific register | Google, Mediatek | Nathan Egge (Google) Chibang Kuan | Zisslpcfi, upstream and downstream dependencies. ABI implications, distro blocker for Android | |
| CT_01_004 | Zfa support (LLVM) | Medium | Completed | Completed | Q2 2023 | Ventana | Craig Topper (SiFive) Jeff Law (Ventana) | ||
| CT_01_005 | Fusion support (LLVM) | Medium | InProgress | NotStarted | Ventana | Jeff Law (Ventana) | Keep fused ops together to improve performance | ||
| CT_01_006 | Stack clash (LLVM) | Medium | Unknown | Unknown | Ventana | Jeff Law (Ventana) | Distro blocker (Android) | ||
| CT_01_007 | CRC Optimization (LLVM) | Medium | Completed | NotStarted | Ventana | Jeff Law (Ventana) | Helps coremark, but more importantly 200+ implementations in distros | ||
| CT_01_008 | Autovectorization (improvements) | High | InProgress | InProgress | PSABI Vector Specification | Q3 2023 | Rivos, Google, Imagination, MediaTek, Andestech, SiFive, Ventana | preames@rivosinc.com rufus@andestech.com jim@andestech.com Chibang Kuan Simon Harvey (Imagination Technologies) Ken Unger? Nathan Egge (Google) efriedma@quicinc.com | Partially lit up in LLVM 16, major development in flight for LLVM 17 which should release in Q3 2023 |
| CT_01_009 | Common syntax for target attribute (LLVM) | Medium | Unknown | Unknown | Allows for specification of target switches on a per-function basis. Prereq for function multiversioning | ||||
| Toolchain-wide items (03) | |||||||||
| CT_03_001 | Binary toolchain packages | Medium | Completed | InProgress | Q2 2023 | Imagination | Simon Harvey (Imagination Technologies) | Updating package hosting for wider sharing | |
| Uncategorized items | |||||||||
| Large Code Model | Medium | InProgress | NotStarted | Rivos, Andestech | Andrew de los Reyes (Rivos) Nelson Chu (Rivos) rufus@andestech.com | Nelson actively working on this (presumably LLVM) | |||
| Shadow Stack (GCC) | Unknown | Unknown | Unknown | Ventana Rivos | Jeff Law (Ventana) Greg McGary | Zisslpcfi, upstream and downstream dependencies. ABI impications, but not a distro blocker for Fedora | |||
| Build Farm | Unknown | Unknown | Unknown | Rivos, Ventana | Andrew de los Reyes (Rivos) Jeff Law (Ventana) | ||||
| SVE Transition Tool | Unknown | Unknown | Unknown | Intel Alibaba | yunhai.syh@alibaba-inc.com | Migration from ARM SVE to RISC-V intrinsics | |||
| If-conversion (LLVM) | Unknown | Unknown | Unknown | Ventana | Jeff Law (Ventana) efriedma@quicinc.com | ZICond target support and middle end improvements | |||
| OpenMP | Unknown | Unknown | Unknown | Microchip | Ken Unger | ||||
| Function Multiversioning | Medium | Unknown | Unknown | Ventana Rivos | Jeff Law (Ventana) | Will have downstream dependencies in some libraries | |||
| Sanitizers (GCC) | Medium | Unknown | Unknown | Ventana | Jeff Law (Ventana) | THis may be OK. So step #1 is to determine state | |||
| Sanitizers (LLVM) | Unknown | Unknown | Unknown | Ventana | Jeff Law (Ventana) | This my be OK. So step #1 is to determine state | |||
| Long branch support (LLVM) | Unknown | Unknown | Unknown | Ventana | Jeff Law (Ventana) | Not sure if this is needed in LLVM. Check | |||
| Code Alignment (GCC) | Medium | Evaluating | Unknown | Ventana | Jeff Law (Ventana) | Not sure if this is needed in LLVM. Check | |||
| Code Alignment (LLVM) | Medium | NotStarted | Unknown | Ventana | Jeff Law (Ventana) | Not sure if this is needed in LLVM. Check | |||
| GCOV Support (GCC) | Medium | NotStarted | Unknown | Ventana | Jeff Law (Ventana) | gcov *might* just work, we need to evaluate | |||