About

Many RISC-V processors support "Instruction Fusion" or "Macro-op Fusion" to improve performance.  The basic idea is certain instructions often show up together in a particular order to implement certain idioms.  For example lui+addi for constant synthesis.  Under the right conditions the processor can "fuse" the two instructions together to reduce the latency of the second instruction, reduce internal processor resources, etc. 

Fusion typically requires the instructions to be consecutive in the instruction stream.   The goal of this project is to define, in a relatively generic way, a method to describe what fusions a particular micro-architecture supports and provide mechanisms to keep those instructions consecutive in the instruction stream.

It is expected that a typical set of supported fusions can reduce the operation count within the processor's execution units by 1-2%.  

Stakeholders/Partners

RISE:

Ventana: Implementation for Veyron V1

External:

Dependencies

Status

Updates

26 Jul 2023

• Venana engineer has go-ahead to start upstreaming additional support for risc-v fusion in LLVM 

01 Jun 2023– Dates on or before June 1 are approximate

• Project reported as priority for 2H23