About

Instruction fusion is an important technique to improve performance of RISC-V systems.  While GCC has support for a common set of instruction fusions, it's believed that additional cases will become more important as new designs come to market. 

1. Store pair fusions.  Right now GCC only supports fusion of two 64 bit stores to aligned addresses.  Newer designs are expected to be able to fuse pairs of same sized stores fairly aggressively.
2. Address calculations with memory references.  Right now GCC supports a limited set fusions of address arithmetic with a memory reference.  Newer designs are expected to be able to fuse nearly every add/shadd with a subsequent memory reference.
3. Zero extended bitfield extractions.  Right now GCC supports a small subset of bitfield extractions when implemented via shifts.  The shift counts are fairly restrictive.
   1. Newer designs are expected to fuse these operations very aggressively.
   2. The compiler should rewrite a right shift + masking off upper bits as a left shift + right logical shift to facilitate fusion.
4. Left shift + add (shift count > 3) are expected to be fusible in the near future.  As are shifts followed by other non-shift ALU ops, including 'w' variants.

Ventana has code to support these cases using the general infrastructure already in the RISC-V GCC backend.  This code just needs to be benchmarked and upstreamed once gcc-16 is open for development.

Stakeholders/Partners

RISE:

Ventana: Jeff Law.  Oversight/guidance

Ventana: Daniel Barboza: Implementation

External:

                     Samsung: Artemiy Volkov

Dependencies

Status

Updates

03 Feb 2025 

• Upstreaming efforts broken out as new 2025 project